Mercurial > sdl-ios-xcode
view src/video/fbcon/riva_regs.h @ 3899:081aecdb0911 SDL-1.2
From: Gabriel Gambetta
To: SDL Mailing List <sdl@libsdl.org>
Date: Fri, 17 Nov 2006 00:39:29 -0200
Subject: [SDL] Alpha blending bug - fixed?
It turns out mm5 never got the correct value. This failed :
[...]
"movd %1, %%mm5\n\t"
: : "m" (amask), "m" (sf->Ashift) );
mm5 got 0xFF000018 instead of 0x00000018. However I did this :
Uint32 ashift = sf->Ashift;
[...]
"movd %1, %%mm5\n\t"
: : "m" (amask), "m" (ashift) );
and everything worked fine.
The only thing I could find out was that ashift is 32-bit aligned but
sf->Ashift isn't:
printf("ashift %8X [%d]\n", &ashift, (int)(&ashift) % 4);
printf("sf->Ashift %8X [%d]\n", &sf->Ashift, (int)(&sf->Ashift) % 4);
ashift at BFF0E0C4 [0]
sf->Ashift at 08AFB9CD [1]
Could this be the problem? If it is, the fix is extremely trivial.
Should I submit a patch?
--Gabriel
author | Ryan C. Gordon <icculus@icculus.org> |
---|---|
date | Tue, 21 Nov 2006 23:17:00 +0000 |
parents | d910939febfa |
children | 782fd950bd46 a1b03ba2fcd0 |
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/* SDL - Simple DirectMedia Layer Copyright (C) 1997-2006 Sam Lantinga This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA Sam Lantinga slouken@libsdl.org */ #include "SDL_config.h" #ifndef _RIVA_REGS_H #define _RIVA_REGS_H /* This information comes from the XFree86 NVidia hardware driver */ /* mapped_io register offsets */ #define PGRAPH_OFFSET 0x00400000 #define FIFO_OFFSET 0x00800000 #define ROP_OFFSET FIFO_OFFSET+0x00000000 #define CLIP_OFFSET FIFO_OFFSET+0x00002000 #define PATT_OFFSET FIFO_OFFSET+0x00004000 #define PIXMAP_OFFSET FIFO_OFFSET+0x00006000 #define BLT_OFFSET FIFO_OFFSET+0x00008000 #define BITMAP_OFFSET FIFO_OFFSET+0x0000A000 #define LINE_OFFSET FIFO_OFFSET+0x0000C000 #define TRI03_OFFSET FIFO_OFFSET+0x0000E000 #define PCIO_OFFSET 0x00601000 #endif /* _RIVA_REGS_H */