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comparison src/stdlib/SDL_stdlib.c @ 1662:782fd950bd46 SDL-1.3

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Revamp of the video system in progress - adding support for multiple displays, multiple windows, and a full video mode selection API. WARNING: None of the video drivers have been updated for the new API yet! The API is still under design and very fluid. The code is now run through a consistent indent format: indent -i4 -nut -nsc -br -ce The headers are being converted to automatically generate doxygen documentation.
author Sam Lantinga <slouken@libsdl.org>
date Sun, 28 May 2006 13:04:16 +0000
parents bb6839704ed6
children 11775724e3fe
comparison
equal deleted inserted replaced
1661:281d3f4870e5 1662:782fd950bd46
31 #if defined(_MSC_VER) 31 #if defined(_MSC_VER)
32 32
33 #ifndef __FLTUSED__ 33 #ifndef __FLTUSED__
34 #define __FLTUSED__ 34 #define __FLTUSED__
35 #ifdef __cplusplus 35 #ifdef __cplusplus
36 extern "C" 36 extern "C"
37 #endif 37 #endif
38 __declspec(selectany) int _fltused=1; 38 __declspec (selectany)
39 int _fltused = 1;
39 #endif 40 #endif
40 41
41 /* Float to long */ 42 /* Float to long */
42 void __declspec(naked) _ftol() 43 void __declspec (naked) _ftol ()
43 { 44 {
44 __asm { 45 __asm {
45 push ebp 46 push ebp mov ebp, esp sub esp, 20 h and esp, 0F FFFFFF0h fld st (0)
46 mov ebp,esp 47 fst dword ptr[esp + 18 h]
47 sub esp,20h 48 fistp qword ptr[esp + 10 h]
48 and esp,0FFFFFFF0h 49 fild qword ptr[esp + 10 h]
49 fld st(0) 50 mov edx, dword ptr[esp + 18 h]
50 fst dword ptr [esp+18h] 51 mov eax, dword ptr[esp + 10 h]
51 fistp qword ptr [esp+10h] 52 test eax, eax
52 fild qword ptr [esp+10h] 53 je integer_QnaN_or_zero
53 mov edx,dword ptr [esp+18h] 54 arg_is_not_integer_QnaN:fsubp st (1), st
54 mov eax,dword ptr [esp+10h] 55 test edx, edx jns positive fstp dword ptr[esp]
55 test eax,eax 56 mov ecx, dword ptr[esp]
56 je integer_QnaN_or_zero 57 xor ecx, 80000000 h
57 arg_is_not_integer_QnaN: 58 add ecx, 7F FFFFFFh adc eax, 0 mov edx, dword ptr[esp + 14 h]
58 fsubp st(1),st 59 adc edx, 0 jmp localexit positive:fstp dword ptr[esp]
59 test edx,edx 60 mov ecx, dword ptr[esp]
60 jns positive 61 add ecx, 7F FFFFFFh sbb eax, 0 mov edx, dword ptr[esp + 14 h]
61 fstp dword ptr [esp] 62 sbb edx, 0
62 mov ecx,dword ptr [esp] 63 jmp localexit integer_QnaN_or_zero:mov edx, dword ptr[esp + 14 h]
63 xor ecx,80000000h 64 test edx, 7F FFFFFFh
64 add ecx,7FFFFFFFh 65 jne arg_is_not_integer_QnaN fstp dword ptr[esp + 18 h]
65 adc eax,0 66 fstp dword ptr[esp + 18 h] localexit:leave ret}
66 mov edx,dword ptr [esp+14h] 67 }
67 adc edx,0 68 void
68 jmp localexit 69 __declspec (naked)
69 positive: 70 _ftol2_sse ()
70 fstp dword ptr [esp] 71 {
71 mov ecx,dword ptr [esp] 72 _ftol ();
72 add ecx,7FFFFFFFh
73 sbb eax,0
74 mov edx,dword ptr [esp+14h]
75 sbb edx,0
76 jmp localexit
77 integer_QnaN_or_zero:
78 mov edx,dword ptr [esp+14h]
79 test edx,7FFFFFFFh
80 jne arg_is_not_integer_QnaN
81 fstp dword ptr [esp+18h]
82 fstp dword ptr [esp+18h]
83 localexit:
84 leave
85 ret
86 }
87 }
88 void __declspec(naked) _ftol2_sse()
89 {
90 _ftol();
91 } 73 }
92 74
93 /* 64-bit math operators for 32-bit systems */ 75 /* 64-bit math operators for 32-bit systems */
94 void __declspec(naked) _allmul() 76 void
95 { 77 __declspec (naked)
96 __asm { 78 _allmul ()
97 push ebp 79 {
98 mov ebp,esp 80 __asm {
99 push edi 81 push ebp
100 push esi 82 mov ebp, esp
101 push ebx 83 push edi
102 sub esp,0Ch 84 push esi push ebx sub esp, 0 Ch mov eax, dword ptr[ebp + 10 h]
103 mov eax,dword ptr [ebp+10h] 85 mov edi, dword ptr[ebp + 8]
104 mov edi,dword ptr [ebp+8] 86 mov ebx, eax mov esi, eax sar esi, 1F h mov eax, dword ptr[ebp + 8]
105 mov ebx,eax 87 mul ebx
106 mov esi,eax 88 imul edi, esi
107 sar esi,1Fh 89 mov ecx, edx
108 mov eax,dword ptr [ebp+8] 90 mov dword ptr[ebp - 18 h], eax mov edx, dword ptr[ebp + 0 Ch]
109 mul ebx 91 add ecx, edi imul ebx, edx mov eax, dword ptr[ebp - 18 h]
110 imul edi,esi 92 lea ebx,[ebx + ecx]
111 mov ecx,edx 93 mov dword ptr[ebp - 14 h], ebx mov edx, dword ptr[ebp - 14 h]
112 mov dword ptr [ebp-18h],eax 94 add esp, 0 Ch pop ebx pop esi pop edi pop ebp ret}
113 mov edx,dword ptr [ebp+0Ch] 95 }
114 add ecx,edi 96 void
115 imul ebx,edx 97 __declspec (naked)
116 mov eax,dword ptr [ebp-18h] 98 _alldiv ()
117 lea ebx,[ebx+ecx] 99 {
118 mov dword ptr [ebp-14h],ebx 100 __asm {
119 mov edx,dword ptr [ebp-14h] 101 push edi push esi push ebx xor edi, edi mov eax, dword ptr[esp + 14 h]
120 add esp,0Ch 102 or eax, eax jge L1 inc edi mov edx, dword ptr[esp + 10 h]
121 pop ebx 103 neg eax
122 pop esi 104 neg edx
123 pop edi 105 sbb eax, 0
124 pop ebp 106 mov dword ptr[esp + 14 h], eax
125 ret 107 mov dword ptr[esp + 10 h], edx L1:mov eax, dword ptr[esp + 1 Ch]
126 } 108 or eax, eax jge L2 inc edi mov edx, dword ptr[esp + 18 h]
127 } 109 neg eax
128 void __declspec(naked) _alldiv() 110 neg edx
129 { 111 sbb eax, 0
130 __asm { 112 mov dword ptr[esp + 1 Ch], eax
131 push edi 113 mov dword ptr[esp + 18 h], edx
132 push esi 114 L2:or eax, eax jne L3 mov ecx, dword ptr[esp + 18 h]
133 push ebx 115 mov eax, dword ptr[esp + 14 h]
134 xor edi,edi 116 xor edx, edx div ecx mov ebx, eax mov eax, dword ptr[esp + 10 h]
135 mov eax,dword ptr [esp+14h] 117 div ecx
136 or eax,eax 118 mov edx, ebx jmp L4 L3:mov ebx, eax mov ecx, dword ptr[esp + 18 h]
137 jge L1 119 mov edx, dword ptr[esp + 14 h]
138 inc edi 120 mov eax, dword ptr[esp + 10 h]
139 mov edx,dword ptr [esp+10h] 121
140 neg eax 122
141 neg edx 123
142 sbb eax,0 124
143 mov dword ptr [esp+14h],eax 125
144 mov dword ptr [esp+10h],edx 126
145 L1: 127
146 mov eax,dword ptr [esp+1Ch] 128 L5:shr ebx, 1
147 or eax,eax 129 rcr ecx, 1
148 jge L2 130 shr edx, 1
149 inc edi 131 rcr eax, 1
150 mov edx,dword ptr [esp+18h] 132 or ebx, ebx jne L5 div ecx mov esi, eax mul dword ptr[esp + 1 Ch]
151 neg eax 133 mov ecx, eax mov eax, dword ptr[esp + 18 h]
152 neg edx 134 mul esi add edx, ecx jb L6 cmp edx, dword ptr[esp + 14 h]
153 sbb eax,0 135 ja L6 jb L7 cmp eax, dword ptr[esp + 10 h]
154 mov dword ptr [esp+1Ch],eax 136 jbe L7
155 mov dword ptr [esp+18h],edx 137 L6:dec esi
156 L2: 138 L7:xor edx, edx
157 or eax,eax 139 mov eax, esi
158 jne L3 140 L4:dec edi
159 mov ecx,dword ptr [esp+18h] 141 jne L8
160 mov eax,dword ptr [esp+14h] 142 neg edx neg eax sbb edx, 0 L8:pop ebx pop esi pop edi ret 10 h}
161 xor edx,edx 143 }
162 div ecx 144 void
163 mov ebx,eax 145 __declspec (naked)
164 mov eax,dword ptr [esp+10h] 146 _aulldiv ()
165 div ecx 147 {
166 mov edx,ebx 148 __asm {
167 jmp L4 149 push ebx push esi mov eax, dword ptr[esp + 18 h]
168 L3: 150 or eax, eax jne L1 mov ecx, dword ptr[esp + 14 h]
169 mov ebx,eax 151 mov eax, dword ptr[esp + 10 h]
170 mov ecx,dword ptr [esp+18h] 152 xor edx, edx div ecx mov ebx, eax mov eax, dword ptr[esp + 0 Ch]
171 mov edx,dword ptr [esp+14h] 153 div ecx
172 mov eax,dword ptr [esp+10h] 154 mov edx, ebx jmp L2 L1:mov ecx, eax mov ebx, dword ptr[esp + 14 h]
173 L5: 155 mov edx, dword ptr[esp + 10 h]
174 shr ebx,1 156 mov eax, dword ptr[esp + 0 Ch]
175 rcr ecx,1 157
176 shr edx,1 158
177 rcr eax,1 159
178 or ebx,ebx 160
179 jne L5 161
180 div ecx 162
181 mov esi,eax 163
182 mul dword ptr [esp+1Ch] 164 L3:shr ecx, 1
183 mov ecx,eax 165 rcr ebx, 1
184 mov eax,dword ptr [esp+18h] 166 shr edx, 1
185 mul esi 167 rcr eax, 1
186 add edx,ecx 168 or ecx, ecx jne L3 div ebx mov esi, eax mul dword ptr[esp + 18 h]
187 jb L6 169 mov ecx, eax mov eax, dword ptr[esp + 14 h]
188 cmp edx,dword ptr [esp+14h] 170 mul esi add edx, ecx jb L4 cmp edx, dword ptr[esp + 10 h]
189 ja L6 171 ja L4 jb L5 cmp eax, dword ptr[esp + 0 Ch]
190 jb L7 172 jbe L5
191 cmp eax,dword ptr [esp+10h] 173 L4:dec esi
192 jbe L7 174 L5:xor edx, edx mov eax, esi L2:pop esi pop ebx ret 10 h}
193 L6: 175 }
194 dec esi 176 void
195 L7: 177 __declspec (naked)
196 xor edx,edx 178 _allrem ()
197 mov eax,esi 179 {
198 L4: 180 __asm {
199 dec edi 181 push ebx push edi xor edi, edi mov eax, dword ptr[esp + 10 h]
200 jne L8 182 or eax, eax jge L1 inc edi mov edx, dword ptr[esp + 0 Ch]
201 neg edx 183 neg eax
202 neg eax 184 neg edx
203 sbb edx,0 185 sbb eax, 0
204 L8: 186 mov dword ptr[esp + 10 h], eax
205 pop ebx 187 mov dword ptr[esp + 0 Ch], edx L1:mov eax, dword ptr[esp + 18 h]
206 pop esi 188 or eax, eax jge L2 mov edx, dword ptr[esp + 14 h]
207 pop edi 189 neg eax
208 ret 10h 190 neg edx
209 } 191 sbb eax, 0
210 } 192 mov dword ptr[esp + 18 h], eax
211 void __declspec(naked) _aulldiv() 193 mov dword ptr[esp + 14 h], edx
212 { 194 L2:or eax, eax jne L3 mov ecx, dword ptr[esp + 14 h]
213 __asm { 195 mov eax, dword ptr[esp + 10 h]
214 push ebx 196 xor edx, edx div ecx mov eax, dword ptr[esp + 0 Ch]
215 push esi 197 div ecx
216 mov eax,dword ptr [esp+18h] 198 mov eax, edx
217 or eax,eax 199 xor edx, edx
218 jne L1 200 dec edi
219 mov ecx,dword ptr [esp+14h] 201 jns L4 jmp L8 L3:mov ebx, eax mov ecx, dword ptr[esp + 14 h]
220 mov eax,dword ptr [esp+10h] 202 mov edx, dword ptr[esp + 10 h]
221 xor edx,edx 203 mov eax, dword ptr[esp + 0 Ch]
222 div ecx 204
223 mov ebx,eax 205
224 mov eax,dword ptr [esp+0Ch] 206
225 div ecx 207
226 mov edx,ebx 208
227 jmp L2 209
228 L1: 210
229 mov ecx,eax 211 L5:shr ebx, 1
230 mov ebx,dword ptr [esp+14h] 212 rcr ecx, 1
231 mov edx,dword ptr [esp+10h] 213 shr edx, 1
232 mov eax,dword ptr [esp+0Ch] 214 rcr eax, 1
233 L3: 215 or ebx, ebx jne L5 div ecx mov ecx, eax mul dword ptr[esp + 18 h]
234 shr ecx,1 216 xchg eax, ecx mul dword ptr[esp + 14 h]
235 rcr ebx,1 217 add edx, ecx jb L6 cmp edx, dword ptr[esp + 10 h]
236 shr edx,1 218 ja L6 jb L7 cmp eax, dword ptr[esp + 0 Ch]
237 rcr eax,1 219 jbe L7 L6:sub eax, dword ptr[esp + 14 h]
238 or ecx,ecx 220 sbb edx, dword ptr[esp + 18 h]
239 jne L3 221 L7:sub eax, dword ptr[esp + 0 Ch]
240 div ebx 222 sbb edx, dword ptr[esp + 10 h]
241 mov esi,eax 223 dec edi
242 mul dword ptr [esp+18h] 224 jns L8 L4:neg edx neg eax sbb edx, 0 L8:pop edi pop ebx ret 10 h}
243 mov ecx,eax 225 }
244 mov eax,dword ptr [esp+14h] 226 void
245 mul esi 227 __declspec (naked)
246 add edx,ecx 228 _aullrem ()
247 jb L4 229 {
248 cmp edx,dword ptr [esp+10h] 230 __asm {
249 ja L4 231 push ebx mov eax, dword ptr[esp + 14 h]
250 jb L5 232 or eax, eax jne L1 mov ecx, dword ptr[esp + 10 h]
251 cmp eax,dword ptr [esp+0Ch] 233 mov eax, dword ptr[esp + 0 Ch]
252 jbe L5 234 xor edx, edx div ecx mov eax, dword ptr[esp + 8]
253 L4: 235 div ecx
254 dec esi 236 mov eax, edx
255 L5: 237 xor edx, edx jmp L2 L1:mov ecx, eax mov ebx, dword ptr[esp + 10 h]
256 xor edx,edx 238 mov edx, dword ptr[esp + 0 Ch]
257 mov eax,esi 239 mov eax, dword ptr[esp + 8]
258 L2: 240
259 pop esi 241
260 pop ebx 242
261 ret 10h 243
262 } 244
263 } 245
264 void __declspec(naked) _allrem() 246
265 { 247 L3:shr ecx, 1
266 __asm { 248 rcr ebx, 1
267 push ebx 249 shr edx, 1
268 push edi 250 rcr eax, 1
269 xor edi,edi 251 or ecx, ecx jne L3 div ebx mov ecx, eax mul dword ptr[esp + 14 h]
270 mov eax,dword ptr [esp+10h] 252 xchg eax, ecx mul dword ptr[esp + 10 h]
271 or eax,eax 253 add edx, ecx jb L4 cmp edx, dword ptr[esp + 0 Ch]
272 jge L1 254 ja L4 jb L5 cmp eax, dword ptr[esp + 8]
273 inc edi 255 jbe L5 L4:sub eax, dword ptr[esp + 10 h]
274 mov edx,dword ptr [esp+0Ch] 256 sbb edx, dword ptr[esp + 14 h]
275 neg eax 257 L5:sub eax, dword ptr[esp + 8]
276 neg edx 258 sbb edx, dword ptr[esp + 0 Ch]
277 sbb eax,0 259 neg edx neg eax sbb edx, 0 L2:pop ebx ret 10 h}
278 mov dword ptr [esp+10h],eax 260 }
279 mov dword ptr [esp+0Ch],edx 261 void
280 L1: 262 __declspec (naked)
281 mov eax,dword ptr [esp+18h] 263 _alldvrm ()
282 or eax,eax 264 {
283 jge L2 265 __asm {
284 mov edx,dword ptr [esp+14h] 266 push edi
285 neg eax 267 push esi
286 neg edx 268 push ebp xor edi, edi xor ebp, ebp mov eax, dword ptr[esp + 14 h]
287 sbb eax,0 269 or eax, eax jge L1 inc edi inc ebp mov edx, dword ptr[esp + 10 h]
288 mov dword ptr [esp+18h],eax 270 neg eax
289 mov dword ptr [esp+14h],edx 271 neg edx
290 L2: 272 sbb eax, 0
291 or eax,eax 273 mov dword ptr[esp + 14 h], eax
292 jne L3 274 mov dword ptr[esp + 10 h], edx L1:mov eax, dword ptr[esp + 1 Ch]
293 mov ecx,dword ptr [esp+14h] 275 or eax, eax jge L2 inc edi mov edx, dword ptr[esp + 18 h]
294 mov eax,dword ptr [esp+10h] 276 neg eax
295 xor edx,edx 277 neg edx
296 div ecx 278 sbb eax, 0
297 mov eax,dword ptr [esp+0Ch] 279 mov dword ptr[esp + 1 Ch], eax
298 div ecx 280 mov dword ptr[esp + 18 h], edx
299 mov eax,edx 281 L2:or eax, eax jne L3 mov ecx, dword ptr[esp + 18 h]
300 xor edx,edx 282 mov eax, dword ptr[esp + 14 h]
301 dec edi 283 xor edx, edx div ecx mov ebx, eax mov eax, dword ptr[esp + 10 h]
302 jns L4 284 div ecx mov esi, eax mov eax, ebx mul dword ptr[esp + 18 h]
303 jmp L8 285 mov ecx, eax mov eax, esi mul dword ptr[esp + 18 h]
304 L3: 286 add edx, ecx jmp L4 L3:mov ebx, eax mov ecx, dword ptr[esp + 18 h]
305 mov ebx,eax 287 mov edx, dword ptr[esp + 14 h]
306 mov ecx,dword ptr [esp+14h] 288 mov eax, dword ptr[esp + 10 h]
307 mov edx,dword ptr [esp+10h] 289
308 mov eax,dword ptr [esp+0Ch] 290
309 L5: 291
310 shr ebx,1 292
311 rcr ecx,1 293
312 shr edx,1 294
313 rcr eax,1 295
314 or ebx,ebx 296 L5:shr ebx, 1
315 jne L5 297 rcr ecx, 1
316 div ecx 298 shr edx, 1
317 mov ecx,eax 299 rcr eax, 1
318 mul dword ptr [esp+18h] 300 or ebx, ebx jne L5 div ecx mov esi, eax mul dword ptr[esp + 1 Ch]
319 xchg eax,ecx 301 mov ecx, eax mov eax, dword ptr[esp + 18 h]
320 mul dword ptr [esp+14h] 302 mul esi add edx, ecx jb L6 cmp edx, dword ptr[esp + 14 h]
321 add edx,ecx 303 ja L6 jb L7 cmp eax, dword ptr[esp + 10 h]
322 jb L6 304 jbe L7 L6:dec esi sub eax, dword ptr[esp + 18 h]
323 cmp edx,dword ptr [esp+10h] 305 sbb edx, dword ptr[esp + 1 Ch]
324 ja L6 306 L7:xor ebx, ebx L4:sub eax, dword ptr[esp + 10 h]
325 jb L7 307 sbb edx, dword ptr[esp + 14 h]
326 cmp eax,dword ptr [esp+0Ch] 308 dec ebp
327 jbe L7 309 jns L9
328 L6: 310 neg edx
329 sub eax,dword ptr [esp+14h] 311 neg eax
330 sbb edx,dword ptr [esp+18h] 312 sbb edx, 0
331 L7: 313 L9:mov ecx, edx
332 sub eax,dword ptr [esp+0Ch] 314 mov edx, ebx
333 sbb edx,dword ptr [esp+10h] 315 mov ebx, ecx
334 dec edi 316 mov ecx, eax
335 jns L8 317 mov eax, esi
336 L4: 318 dec edi
337 neg edx 319 jne L8
338 neg eax 320 neg edx neg eax sbb edx, 0 L8:pop ebp pop esi pop edi ret 10 h}
339 sbb edx,0 321 }
340 L8: 322 void
341 pop edi 323 __declspec (naked)
342 pop ebx 324 _aulldvrm ()
343 ret 10h 325 {
344 } 326 __asm {
345 } 327 push esi mov eax, dword ptr[esp + 14 h]
346 void __declspec(naked) _aullrem() 328 or eax, eax jne L1 mov ecx, dword ptr[esp + 10 h]
347 { 329 mov eax, dword ptr[esp + 0 Ch]
348 __asm { 330 xor edx, edx div ecx mov ebx, eax mov eax, dword ptr[esp + 8]
349 push ebx 331 div ecx mov esi, eax mov eax, ebx mul dword ptr[esp + 10 h]
350 mov eax,dword ptr [esp+14h] 332 mov ecx, eax mov eax, esi mul dword ptr[esp + 10 h]
351 or eax,eax 333 add edx, ecx jmp L2 L1:mov ecx, eax mov ebx, dword ptr[esp + 10 h]
352 jne L1 334 mov edx, dword ptr[esp + 0 Ch]
353 mov ecx,dword ptr [esp+10h] 335 mov eax, dword ptr[esp + 8]
354 mov eax,dword ptr [esp+0Ch] 336
355 xor edx,edx 337
356 div ecx 338
357 mov eax,dword ptr [esp+8] 339
358 div ecx 340
359 mov eax,edx 341
360 xor edx,edx 342
361 jmp L2 343 L3:shr ecx, 1
362 L1: 344 rcr ebx, 1
363 mov ecx,eax 345 shr edx, 1
364 mov ebx,dword ptr [esp+10h] 346 rcr eax, 1
365 mov edx,dword ptr [esp+0Ch] 347 or ecx, ecx jne L3 div ebx mov esi, eax mul dword ptr[esp + 14 h]
366 mov eax,dword ptr [esp+8] 348 mov ecx, eax mov eax, dword ptr[esp + 10 h]
367 L3: 349 mul esi add edx, ecx jb L4 cmp edx, dword ptr[esp + 0 Ch]
368 shr ecx,1 350 ja L4 jb L5 cmp eax, dword ptr[esp + 8]
369 rcr ebx,1 351 jbe L5 L4:dec esi sub eax, dword ptr[esp + 10 h]
370 shr edx,1 352 sbb edx, dword ptr[esp + 14 h]
371 rcr eax,1 353 L5:xor ebx, ebx L2:sub eax, dword ptr[esp + 8]
372 or ecx,ecx 354 sbb edx, dword ptr[esp + 0 Ch]
373 jne L3 355 neg edx
374 div ebx 356 neg eax
375 mov ecx,eax 357 sbb edx, 0
376 mul dword ptr [esp+14h] 358 mov ecx, edx
377 xchg eax,ecx 359 mov edx, ebx
378 mul dword ptr [esp+10h] 360 mov ebx, ecx mov ecx, eax mov eax, esi pop esi ret 10 h}
379 add edx,ecx 361 }
380 jb L4 362 void
381 cmp edx,dword ptr [esp+0Ch] 363 __declspec (naked)
382 ja L4 364 _allshl ()
383 jb L5 365 {
384 cmp eax,dword ptr [esp+8] 366 __asm {
385 jbe L5 367 cmp cl, 40 h
386 L4: 368 jae RETZERO
387 sub eax,dword ptr [esp+10h] 369 cmp cl, 20 h
388 sbb edx,dword ptr [esp+14h] 370 jae MORE32
389 L5: 371 shld edx, eax, cl
390 sub eax,dword ptr [esp+8] 372 shl eax, cl
391 sbb edx,dword ptr [esp+0Ch] 373 ret
392 neg edx 374 MORE32:mov edx, eax
393 neg eax 375 xor eax, eax
394 sbb edx,0 376 and cl, 1F h
395 L2: 377 shl edx, cl ret RETZERO:xor eax, eax xor edx, edx ret}
396 pop ebx 378 }
397 ret 10h 379 void
398 } 380 __declspec (naked)
399 } 381 _aullshr ()
400 void __declspec(naked) _alldvrm() 382 {
401 { 383 __asm {
402 __asm { 384 cmp cl, 40 h
403 push edi 385 jae RETZERO
404 push esi 386 cmp cl, 20 h
405 push ebp 387 jae MORE32
406 xor edi,edi 388 shrd eax, edx, cl
407 xor ebp,ebp 389 shr edx, cl
408 mov eax,dword ptr [esp+14h] 390 ret
409 or eax,eax 391 MORE32:mov eax, edx
410 jge L1 392 xor edx, edx
411 inc edi 393 and cl, 1F h
412 inc ebp 394 shr eax, cl ret RETZERO:xor eax, eax xor edx, edx ret}
413 mov edx,dword ptr [esp+10h] 395 }
414 neg eax 396
415 neg edx 397 #endif /* MSC_VER */
416 sbb eax,0 398
417 mov dword ptr [esp+14h],eax 399 #endif /* !HAVE_LIBC */
418 mov dword ptr [esp+10h],edx 400 /* vi: set ts=4 sw=4 expandtab: */
419 L1:
420 mov eax,dword ptr [esp+1Ch]
421 or eax,eax
422 jge L2
423 inc edi
424 mov edx,dword ptr [esp+18h]
425 neg eax
426 neg edx
427 sbb eax,0
428 mov dword ptr [esp+1Ch],eax
429 mov dword ptr [esp+18h],edx
430 L2:
431 or eax,eax
432 jne L3
433 mov ecx,dword ptr [esp+18h]
434 mov eax,dword ptr [esp+14h]
435 xor edx,edx
436 div ecx
437 mov ebx,eax
438 mov eax,dword ptr [esp+10h]
439 div ecx
440 mov esi,eax
441 mov eax,ebx
442 mul dword ptr [esp+18h]
443 mov ecx,eax
444 mov eax,esi
445 mul dword ptr [esp+18h]
446 add edx,ecx
447 jmp L4
448 L3:
449 mov ebx,eax
450 mov ecx,dword ptr [esp+18h]
451 mov edx,dword ptr [esp+14h]
452 mov eax,dword ptr [esp+10h]
453 L5:
454 shr ebx,1
455 rcr ecx,1
456 shr edx,1
457 rcr eax,1
458 or ebx,ebx
459 jne L5
460 div ecx
461 mov esi,eax
462 mul dword ptr [esp+1Ch]
463 mov ecx,eax
464 mov eax,dword ptr [esp+18h]
465 mul esi
466 add edx,ecx
467 jb L6
468 cmp edx,dword ptr [esp+14h]
469 ja L6
470 jb L7
471 cmp eax,dword ptr [esp+10h]
472 jbe L7
473 L6:
474 dec esi
475 sub eax,dword ptr [esp+18h]
476 sbb edx,dword ptr [esp+1Ch]
477 L7:
478 xor ebx,ebx
479 L4:
480 sub eax,dword ptr [esp+10h]
481 sbb edx,dword ptr [esp+14h]
482 dec ebp
483 jns L9
484 neg edx
485 neg eax
486 sbb edx,0
487 L9:
488 mov ecx,edx
489 mov edx,ebx
490 mov ebx,ecx
491 mov ecx,eax
492 mov eax,esi
493 dec edi
494 jne L8
495 neg edx
496 neg eax
497 sbb edx,0
498 L8:
499 pop ebp
500 pop esi
501 pop edi
502 ret 10h
503 }
504 }
505 void __declspec(naked) _aulldvrm()
506 {
507 __asm {
508 push esi
509 mov eax,dword ptr [esp+14h]
510 or eax,eax
511 jne L1
512 mov ecx,dword ptr [esp+10h]
513 mov eax,dword ptr [esp+0Ch]
514 xor edx,edx
515 div ecx
516 mov ebx,eax
517 mov eax,dword ptr [esp+8]
518 div ecx
519 mov esi,eax
520 mov eax,ebx
521 mul dword ptr [esp+10h]
522 mov ecx,eax
523 mov eax,esi
524 mul dword ptr [esp+10h]
525 add edx,ecx
526 jmp L2
527 L1:
528 mov ecx,eax
529 mov ebx,dword ptr [esp+10h]
530 mov edx,dword ptr [esp+0Ch]
531 mov eax,dword ptr [esp+8]
532 L3:
533 shr ecx,1
534 rcr ebx,1
535 shr edx,1
536 rcr eax,1
537 or ecx,ecx
538 jne L3
539 div ebx
540 mov esi,eax
541 mul dword ptr [esp+14h]
542 mov ecx,eax
543 mov eax,dword ptr [esp+10h]
544 mul esi
545 add edx,ecx
546 jb L4
547 cmp edx,dword ptr [esp+0Ch]
548 ja L4
549 jb L5
550 cmp eax,dword ptr [esp+8]
551 jbe L5
552 L4:
553 dec esi
554 sub eax,dword ptr [esp+10h]
555 sbb edx,dword ptr [esp+14h]
556 L5:
557 xor ebx,ebx
558 L2:
559 sub eax,dword ptr [esp+8]
560 sbb edx,dword ptr [esp+0Ch]
561 neg edx
562 neg eax
563 sbb edx,0
564 mov ecx,edx
565 mov edx,ebx
566 mov ebx,ecx
567 mov ecx,eax
568 mov eax,esi
569 pop esi
570 ret 10h
571 }
572 }
573 void __declspec(naked) _allshl()
574 {
575 __asm {
576 cmp cl,40h
577 jae RETZERO
578 cmp cl,20h
579 jae MORE32
580 shld edx,eax,cl
581 shl eax,cl
582 ret
583 MORE32:
584 mov edx,eax
585 xor eax,eax
586 and cl,1Fh
587 shl edx,cl
588 ret
589 RETZERO:
590 xor eax,eax
591 xor edx,edx
592 ret
593 }
594 }
595 void __declspec(naked) _aullshr()
596 {
597 __asm {
598 cmp cl,40h
599 jae RETZERO
600 cmp cl,20h
601 jae MORE32
602 shrd eax,edx,cl
603 shr edx,cl
604 ret
605 MORE32:
606 mov eax,edx
607 xor edx,edx
608 and cl,1Fh
609 shr eax,cl
610 ret
611 RETZERO:
612 xor eax,eax
613 xor edx,edx
614 ret
615 }
616 }
617
618 #endif /* MSC_VER */
619
620 #endif /* !HAVE_LIBC */