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comparison src/video/fbcon/riva_mmio.h @ 133:5d4bafca35cd

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Added support for hardware accelerated NVidia driver on framebuffer console Still missing colorkey and alpha blit support
author Sam Lantinga <slouken@libsdl.org>
date Tue, 31 Jul 2001 20:08:51 +0000
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children 782fd950bd46
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132:2604a7be65af 133:5d4bafca35cd
1 /***************************************************************************\
2 |* *|
3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
4 |* *|
5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
6 |* international laws. Users and possessors of this source code are *|
7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
8 |* use this code in individual and commercial software. *|
9 |* *|
10 |* Any use of this source code must include, in the user documenta- *|
11 |* tion and internal comments to the code, notices to the end user *|
12 |* as follows: *|
13 |* *|
14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
15 |* *|
16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
27 |* *|
28 |* U.S. Government End Users. This source code is a "commercial *|
29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
30 |* consisting of "commercial computer software" and "commercial *|
31 |* computer software documentation," as such terms are used in *|
32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
35 |* all U.S. Government End Users acquire the source code with only *|
36 |* those rights set forth herein. *|
37 |* *|
38 \***************************************************************************/
39
40 #ifndef __RIVA_HW_H__
41 #define __RIVA_HW_H__
42 #define RIVA_SW_VERSION 0x00010003
43
44 /*
45 * Typedefs to force certain sized values.
46 */
47 typedef Uint8 U008;
48 typedef Uint16 U016;
49 typedef Uint32 U032;
50
51 /*
52 * HW access macros.
53 */
54 #define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d))
55 #define NV_RD08(p,i) (((U008 *)(p))[i])
56 #define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d))
57 #define NV_RD16(p,i) (((U016 *)(p))[(i)/2])
58 #define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d))
59 #define NV_RD32(p,i) (((U032 *)(p))[(i)/4])
60 #define VGA_WR08(p,i,d) NV_WR08(p,i,d)
61 #define VGA_RD08(p,i) NV_RD08(p,i)
62
63 /*
64 * Define supported architectures.
65 */
66 #define NV_ARCH_03 0x03
67 #define NV_ARCH_04 0x04
68 #define NV_ARCH_10 0x10
69 /***************************************************************************\
70 * *
71 * FIFO registers. *
72 * *
73 \***************************************************************************/
74
75 /*
76 * Raster OPeration. Windows style ROP3.
77 */
78 typedef volatile struct
79 {
80 U032 reserved00[4];
81 U016 FifoFree;
82 U016 Nop;
83 U032 reserved01[0x0BB];
84 U032 Rop3;
85 } RivaRop;
86 /*
87 * 8X8 Monochrome pattern.
88 */
89 typedef volatile struct
90 {
91 U032 reserved00[4];
92 U016 FifoFree;
93 U016 Nop;
94 U032 reserved01[0x0BD];
95 U032 Shape;
96 U032 reserved03[0x001];
97 U032 Color0;
98 U032 Color1;
99 U032 Monochrome[2];
100 } RivaPattern;
101 /*
102 * Scissor clip rectangle.
103 */
104 typedef volatile struct
105 {
106 U032 reserved00[4];
107 U016 FifoFree;
108 U016 Nop;
109 U032 reserved01[0x0BB];
110 U032 TopLeft;
111 U032 WidthHeight;
112 } RivaClip;
113 /*
114 * 2D filled rectangle.
115 */
116 typedef volatile struct
117 {
118 U032 reserved00[4];
119 U016 FifoFree;
120 U016 Nop[1];
121 U032 reserved01[0x0BC];
122 U032 Color;
123 U032 reserved03[0x03E];
124 U032 TopLeft;
125 U032 WidthHeight;
126 } RivaRectangle;
127 /*
128 * 2D screen-screen BLT.
129 */
130 typedef volatile struct
131 {
132 U032 reserved00[4];
133 U016 FifoFree;
134 U016 Nop;
135 U032 reserved01[0x0BB];
136 U032 TopLeftSrc;
137 U032 TopLeftDst;
138 U032 WidthHeight;
139 } RivaScreenBlt;
140 /*
141 * 2D pixel BLT.
142 */
143 typedef volatile struct
144 {
145 U032 reserved00[4];
146 U016 FifoFree;
147 U016 Nop[1];
148 U032 reserved01[0x0BC];
149 U032 TopLeft;
150 U032 WidthHeight;
151 U032 WidthHeightIn;
152 U032 reserved02[0x03C];
153 U032 Pixels;
154 } RivaPixmap;
155 /*
156 * Filled rectangle combined with monochrome expand. Useful for glyphs.
157 */
158 typedef volatile struct
159 {
160 U032 reserved00[4];
161 U016 FifoFree;
162 U016 Nop;
163 U032 reserved01[0x0BB];
164 U032 reserved03[(0x040)-1];
165 U032 Color1A;
166 struct
167 {
168 U032 TopLeft;
169 U032 WidthHeight;
170 } UnclippedRectangle[64];
171 U032 reserved04[(0x080)-3];
172 struct
173 {
174 U032 TopLeft;
175 U032 BottomRight;
176 } ClipB;
177 U032 Color1B;
178 struct
179 {
180 U032 TopLeft;
181 U032 BottomRight;
182 } ClippedRectangle[64];
183 U032 reserved05[(0x080)-5];
184 struct
185 {
186 U032 TopLeft;
187 U032 BottomRight;
188 } ClipC;
189 U032 Color1C;
190 U032 WidthHeightC;
191 U032 PointC;
192 U032 MonochromeData1C;
193 U032 reserved06[(0x080)+121];
194 struct
195 {
196 U032 TopLeft;
197 U032 BottomRight;
198 } ClipD;
199 U032 Color1D;
200 U032 WidthHeightInD;
201 U032 WidthHeightOutD;
202 U032 PointD;
203 U032 MonochromeData1D;
204 U032 reserved07[(0x080)+120];
205 struct
206 {
207 U032 TopLeft;
208 U032 BottomRight;
209 } ClipE;
210 U032 Color0E;
211 U032 Color1E;
212 U032 WidthHeightInE;
213 U032 WidthHeightOutE;
214 U032 PointE;
215 U032 MonochromeData01E;
216 } RivaBitmap;
217 /*
218 * 3D textured, Z buffered triangle.
219 */
220 typedef volatile struct
221 {
222 U032 reserved00[4];
223 U016 FifoFree;
224 U016 Nop;
225 U032 reserved01[0x0BC];
226 U032 TextureOffset;
227 U032 TextureFormat;
228 U032 TextureFilter;
229 U032 FogColor;
230 /* This is a problem on LynxOS */
231 #ifdef Control
232 #undef Control
233 #endif
234 U032 Control;
235 U032 AlphaTest;
236 U032 reserved02[0x339];
237 U032 FogAndIndex;
238 U032 Color;
239 float ScreenX;
240 float ScreenY;
241 float ScreenZ;
242 float EyeM;
243 float TextureS;
244 float TextureT;
245 } RivaTexturedTriangle03;
246 typedef volatile struct
247 {
248 U032 reserved00[4];
249 U016 FifoFree;
250 U016 Nop;
251 U032 reserved01[0x0BB];
252 U032 ColorKey;
253 U032 TextureOffset;
254 U032 TextureFormat;
255 U032 TextureFilter;
256 U032 Blend;
257 /* This is a problem on LynxOS */
258 #ifdef Control
259 #undef Control
260 #endif
261 U032 Control;
262 U032 FogColor;
263 U032 reserved02[0x39];
264 struct
265 {
266 float ScreenX;
267 float ScreenY;
268 float ScreenZ;
269 float EyeM;
270 U032 Color;
271 U032 Specular;
272 float TextureS;
273 float TextureT;
274 } Vertex[16];
275 U032 DrawTriangle3D;
276 } RivaTexturedTriangle05;
277 /*
278 * 2D line.
279 */
280 typedef volatile struct
281 {
282 U032 reserved00[4];
283 U016 FifoFree;
284 U016 Nop[1];
285 U032 reserved01[0x0BC];
286 U032 Color; /* source color 0304-0307*/
287 U032 Reserved02[0x03e];
288 struct { /* start aliased methods in array 0400- */
289 U032 point0; /* y_x S16_S16 in pixels 0- 3*/
290 U032 point1; /* y_x S16_S16 in pixels 4- 7*/
291 } Lin[16]; /* end of aliased methods in array -047f*/
292 struct { /* start aliased methods in array 0480- */
293 U032 point0X; /* in pixels, 0 at left 0- 3*/
294 U032 point0Y; /* in pixels, 0 at top 4- 7*/
295 U032 point1X; /* in pixels, 0 at left 8- b*/
296 U032 point1Y; /* in pixels, 0 at top c- f*/
297 } Lin32[8]; /* end of aliased methods in array -04ff*/
298 U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f*/
299 struct { /* start aliased methods in array 0580- */
300 U032 x; /* in pixels, 0 at left 0- 3*/
301 U032 y; /* in pixels, 0 at top 4- 7*/
302 } PolyLin32[16]; /* end of aliased methods in array -05ff*/
303 struct { /* start aliased methods in array 0600- */
304 U032 color; /* source color 0- 3*/
305 U032 point; /* y_x S16_S16 in pixels 4- 7*/
306 } ColorPolyLin[16]; /* end of aliased methods in array -067f*/
307 } RivaLine;
308 /*
309 * 2D/3D surfaces
310 */
311 typedef volatile struct
312 {
313 U032 reserved00[4];
314 U016 FifoFree;
315 U016 Nop;
316 U032 reserved01[0x0BE];
317 U032 Offset;
318 } RivaSurface;
319 typedef volatile struct
320 {
321 U032 reserved00[4];
322 U016 FifoFree;
323 U016 Nop;
324 U032 reserved01[0x0BD];
325 U032 Pitch;
326 U032 RenderBufferOffset;
327 U032 ZBufferOffset;
328 } RivaSurface3D;
329
330 /***************************************************************************\
331 * *
332 * Virtualized RIVA H/W interface. *
333 * *
334 \***************************************************************************/
335
336 struct _riva_hw_inst;
337 struct _riva_hw_state;
338 /*
339 * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
340 */
341 typedef struct _riva_hw_inst
342 {
343 /*
344 * Chip specific settings.
345 */
346 U032 Architecture;
347 U032 Version;
348 U032 CrystalFreqKHz;
349 U032 RamAmountKBytes;
350 U032 MaxVClockFreqKHz;
351 U032 RamBandwidthKBytesPerSec;
352 U032 EnableIRQ;
353 U032 IO;
354 U032 VBlankBit;
355 U032 FifoFreeCount;
356 U032 FifoEmptyCount;
357 /*
358 * Non-FIFO registers.
359 */
360 volatile U032 *PCRTC;
361 volatile U032 *PRAMDAC;
362 volatile U032 *PFB;
363 volatile U032 *PFIFO;
364 volatile U032 *PGRAPH;
365 volatile U032 *PEXTDEV;
366 volatile U032 *PTIMER;
367 volatile U032 *PMC;
368 volatile U032 *PRAMIN;
369 volatile U032 *FIFO;
370 volatile U032 *CURSOR;
371 volatile U032 *CURSORPOS;
372 volatile U032 *VBLANKENABLE;
373 volatile U032 *VBLANK;
374 volatile U008 *PCIO;
375 volatile U008 *PVIO;
376 volatile U008 *PDIO;
377 /*
378 * Common chip functions.
379 */
380 int (*Busy)(struct _riva_hw_inst *);
381 void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int,int,int,int,int,int,int,int,int);
382 void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
383 void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
384 void (*SetStartAddress)(struct _riva_hw_inst *,U032);
385 void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
386 void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
387 int (*ShowHideCursor)(struct _riva_hw_inst *,int);
388 void (*LockUnlock)(struct _riva_hw_inst *, int);
389 /*
390 * Current extended mode settings.
391 */
392 struct _riva_hw_state *CurrentState;
393 /*
394 * FIFO registers.
395 */
396 RivaRop *Rop;
397 RivaPattern *Patt;
398 RivaClip *Clip;
399 RivaPixmap *Pixmap;
400 RivaScreenBlt *Blt;
401 RivaBitmap *Bitmap;
402 RivaLine *Line;
403 RivaTexturedTriangle03 *Tri03;
404 RivaTexturedTriangle05 *Tri05;
405 } RIVA_HW_INST;
406 /*
407 * Extended mode state information.
408 */
409 typedef struct _riva_hw_state
410 {
411 U032 bpp;
412 U032 width;
413 U032 height;
414 U032 repaint0;
415 U032 repaint1;
416 U032 screen;
417 U032 pixel;
418 U032 horiz;
419 U032 arbitration0;
420 U032 arbitration1;
421 U032 vpll;
422 U032 pllsel;
423 U032 general;
424 U032 config;
425 U032 cursor0;
426 U032 cursor1;
427 U032 cursor2;
428 U032 offset0;
429 U032 offset1;
430 U032 offset2;
431 U032 offset3;
432 U032 pitch0;
433 U032 pitch1;
434 U032 pitch2;
435 U032 pitch3;
436 } RIVA_HW_STATE;
437
438 /*
439 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
440 */
441
442 #define RIVA_FIFO_FREE(hwptr,cnt) \
443 { \
444 while (FifoFreeCount < (cnt)) \
445 FifoFreeCount = hwptr->FifoFree >> 2; \
446 FifoFreeCount -= (cnt); \
447 }
448 #endif /* __RIVA_HW_H__ */
449