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comparison test/testatomic.c @ 5117:427998ff3bcf

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Added cache line size info in SDL_cpuinfo.h I also added an implementation to dynamically query it, but didn't expose it since most x86 CPUs have an L1 cache line size of 64 bytes.
author Sam Lantinga <slouken@libsdl.org>
date Thu, 27 Jan 2011 16:46:15 -0800
parents e337f792c6a7
children 02b860cbc7ce
comparison
equal deleted inserted replaced
5116:e337f792c6a7 5117:427998ff3bcf
241 241
242 #define NUM_READERS 4 242 #define NUM_READERS 4
243 #define NUM_WRITERS 4 243 #define NUM_WRITERS 4
244 #define EVENTS_PER_WRITER 1000000 244 #define EVENTS_PER_WRITER 1000000
245 245
246 /* A decent guess for the size of a cache line on this architecture */
247 #define CACHELINE 64
248
249 /* The number of entries must be a power of 2 */ 246 /* The number of entries must be a power of 2 */
250 #define MAX_ENTRIES 256 247 #define MAX_ENTRIES 256
251 #define WRAP_MASK (MAX_ENTRIES-1) 248 #define WRAP_MASK (MAX_ENTRIES-1)
252 249
253 typedef struct 250 typedef struct
258 255
259 typedef struct 256 typedef struct
260 { 257 {
261 SDL_EventQueueEntry entries[MAX_ENTRIES]; 258 SDL_EventQueueEntry entries[MAX_ENTRIES];
262 259
263 char cache_pad1[CACHELINE-((sizeof(SDL_EventQueueEntry)*MAX_ENTRIES)%CACHELINE)]; 260 char cache_pad1[SDL_CACHELINE_SIZE-((sizeof(SDL_EventQueueEntry)*MAX_ENTRIES)%SDL_CACHELINE_SIZE)];
264 261
265 SDL_atomic_t enqueue_pos; 262 SDL_atomic_t enqueue_pos;
266 263
267 char cache_pad2[CACHELINE-sizeof(SDL_atomic_t)]; 264 char cache_pad2[SDL_CACHELINE_SIZE-sizeof(SDL_atomic_t)];
268 265
269 SDL_atomic_t dequeue_pos; 266 SDL_atomic_t dequeue_pos;
270 267
271 char cache_pad3[CACHELINE-sizeof(SDL_atomic_t)]; 268 char cache_pad3[SDL_CACHELINE_SIZE-sizeof(SDL_atomic_t)];
272 269
273 #ifdef TEST_SPINLOCK_FIFO 270 #ifdef TEST_SPINLOCK_FIFO
274 SDL_SpinLock lock; 271 SDL_SpinLock lock;
275 SDL_atomic_t rwcount; 272 SDL_atomic_t rwcount;
276 SDL_atomic_t watcher; 273 SDL_atomic_t watcher;
277 274
278 char cache_pad4[CACHELINE-sizeof(SDL_SpinLock)-2*sizeof(SDL_atomic_t)]; 275 char cache_pad4[SDL_CACHELINE_SIZE-sizeof(SDL_SpinLock)-2*sizeof(SDL_atomic_t)];
279 #endif 276 #endif
280 277
281 volatile SDL_bool active; 278 volatile SDL_bool active;
282 279
283 /* Only needed for the mutex test */ 280 /* Only needed for the mutex test */
468 465
469 typedef struct 466 typedef struct
470 { 467 {
471 SDL_EventQueue *queue; 468 SDL_EventQueue *queue;
472 int index; 469 int index;
473 char padding1[CACHELINE-(sizeof(SDL_EventQueue*)+sizeof(int))%CACHELINE]; 470 char padding1[SDL_CACHELINE_SIZE-(sizeof(SDL_EventQueue*)+sizeof(int))%SDL_CACHELINE_SIZE];
474 int waits; 471 int waits;
475 SDL_bool lock_free; 472 SDL_bool lock_free;
476 char padding2[CACHELINE-sizeof(int)-sizeof(SDL_bool)]; 473 char padding2[SDL_CACHELINE_SIZE-sizeof(int)-sizeof(SDL_bool)];
477 } WriterData; 474 } WriterData;
478 475
479 typedef struct 476 typedef struct
480 { 477 {
481 SDL_EventQueue *queue; 478 SDL_EventQueue *queue;
482 int counters[NUM_WRITERS]; 479 int counters[NUM_WRITERS];
483 int waits; 480 int waits;
484 SDL_bool lock_free; 481 SDL_bool lock_free;
485 char padding[CACHELINE-(sizeof(SDL_EventQueue*)+sizeof(int)*NUM_WRITERS+sizeof(int)+sizeof(SDL_bool))%CACHELINE]; 482 char padding[SDL_CACHELINE_SIZE-(sizeof(SDL_EventQueue*)+sizeof(int)*NUM_WRITERS+sizeof(int)+sizeof(SDL_bool))%SDL_CACHELINE_SIZE];
486 } ReaderData; 483 } ReaderData;
487 484
488 static int FIFO_Writer(void* _data) 485 static int FIFO_Writer(void* _data)
489 { 486 {
490 WriterData *data = (WriterData *)_data; 487 WriterData *data = (WriterData *)_data;