Mercurial > sdl-ios-xcode
annotate src/video/mmx.h @ 5130:f2c2f0ecba5f
Fixed bug #1111
kwm@rainbow-runner.nl 2011-01-30 06:28:27 PST
Created attachment 562 [details]
Build fix with clang.
When building sdl 1.2.14 with the Clang compiler http://clang.llvm.org .
The build fails in src/video/mmx.h with the following error:
--------------------------------------------------
./src/video/SDL_RLEaccel.c:831:5: error: invalid operand for instruction
CHOOSE_BLIT(RLECLIPBLIT, alpha, fmt);
^
./src/video/SDL_RLEaccel.c:831:17: note: instantiated from:
CHOOSE_BLIT(RLECLIPBLIT, alpha, fmt);
^
./src/video/SDL_RLEaccel.c:831:5: note: instantiated from:
CHOOSE_BLIT(RLECLIPBLIT, alpha, fmt);
^
./src/video/SDL_RLEaccel.c:647:23: note: instantiated from:
blitter(2, Uint8, ALPHA_BLIT16_565MMX); \
^
./src/video/SDL_RLEaccel.c:282:4: note: instantiated from:
movq_r2m(mm3, *dstp); \
^
In file included from ./src/video/SDL_RLEaccel.c:99:
./src/video/mmx.h:379:28: note: instantiated from:
#define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
^
<scratch space>:192:1: note: instantiated from:
"movq"
^
<inline asm>:1:2: note: instantiated into assembly here
movq %mm3, %dx
^
--------------------------------------------------
According to the clang developers this is a invalid inline assembly.
Using the attached patch from the last commit in the below bug report fixes the
compile.
More details from: http://llvm.org/bugs/show_bug.cgi?id=6730
author | Sam Lantinga <slouken@libsdl.org> |
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date | Sun, 30 Jan 2011 13:42:05 -0800 |
parents | c121d94672cb |
children |
rev | line source |
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689
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1 /* mmx.h |
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2 |
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3 MultiMedia eXtensions GCC interface library for IA32. |
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4 |
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5 To use this library, simply include this header file |
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6 and compile with GCC. You MUST have inlining enabled |
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7 in order for mmx_ok() to work; this can be done by |
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8 simply using -O on the GCC command line. |
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9 |
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10 Compiling with -DMMX_TRACE will cause detailed trace |
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11 output to be sent to stderr for each mmx operation. |
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12 This adds lots of code, and obviously slows execution to |
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13 a crawl, but can be very useful for debugging. |
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14 |
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15 THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY |
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16 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT |
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17 LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY |
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18 AND FITNESS FOR ANY PARTICULAR PURPOSE. |
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19 |
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20 1997-99 by H. Dietz and R. Fisher |
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21 |
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22 Notes: |
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23 It appears that the latest gas has the pand problem fixed, therefore |
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24 I'll undefine BROKEN_PAND by default. |
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25 */ |
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26 |
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27 #ifndef _MMX_H |
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28 #define _MMX_H |
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29 |
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30 |
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31 /* Warning: at this writing, the version of GAS packaged |
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32 with most Linux distributions does not handle the |
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33 parallel AND operation mnemonic correctly. If the |
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34 symbol BROKEN_PAND is defined, a slower alternative |
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35 coding will be used. If execution of mmxtest results |
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36 in an illegal instruction fault, define this symbol. |
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37 */ |
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38 #undef BROKEN_PAND |
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39 |
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40 |
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41 /* The type of an value that fits in an MMX register |
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42 (note that long long constant values MUST be suffixed |
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43 by LL and unsigned long long values by ULL, lest |
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44 they be truncated by the compiler) |
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45 */ |
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46 typedef union |
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47 { |
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48 long long q; /* Quadword (64-bit) value */ |
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49 unsigned long long uq; /* Unsigned Quadword */ |
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50 int d[2]; /* 2 Doubleword (32-bit) values */ |
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51 unsigned int ud[2]; /* 2 Unsigned Doubleword */ |
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52 short w[4]; /* 4 Word (16-bit) values */ |
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53 unsigned short uw[4]; /* 4 Unsigned Word */ |
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54 char b[8]; /* 8 Byte (8-bit) values */ |
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55 unsigned char ub[8]; /* 8 Unsigned Byte */ |
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56 float s[2]; /* Single-precision (32-bit) value */ |
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57 } __attribute__ ((aligned(8))) mmx_t; /* On an 8-byte (64-bit) boundary */ |
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58 |
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59 |
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60 #if 0 |
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61 /* Function to test if multimedia instructions are supported... |
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62 */ |
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63 inline extern int |
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64 mm_support(void) |
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65 { |
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66 /* Returns 1 if MMX instructions are supported, |
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67 3 if Cyrix MMX and Extended MMX instructions are supported |
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68 5 if AMD MMX and 3DNow! instructions are supported |
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69 0 if hardware does not support any of these |
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70 */ |
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71 register int rval = 0; |
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72 |
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73 __asm__ __volatile__( |
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74 /* See if CPUID instruction is supported ... */ |
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75 /* ... Get copies of EFLAGS into eax and ecx */ |
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76 "pushf\n\t" |
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77 "popl %%eax\n\t" "movl %%eax, %%ecx\n\t" |
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78 /* ... Toggle the ID bit in one copy and store */ |
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79 /* to the EFLAGS reg */ |
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80 "xorl $0x200000, %%eax\n\t" |
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81 "push %%eax\n\t" "popf\n\t" |
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82 /* ... Get the (hopefully modified) EFLAGS */ |
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83 "pushf\n\t" "popl %%eax\n\t" |
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84 /* ... Compare and test result */ |
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85 "xorl %%eax, %%ecx\n\t" "testl $0x200000, %%ecx\n\t" "jz NotSupported1\n\t" /* CPUID not supported */ |
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86 /* Get standard CPUID information, and |
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87 go to a specific vendor section */ |
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88 "movl $0, %%eax\n\t" "cpuid\n\t" |
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89 /* Check for Intel */ |
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90 "cmpl $0x756e6547, %%ebx\n\t" |
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91 "jne TryAMD\n\t" |
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92 "cmpl $0x49656e69, %%edx\n\t" |
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93 "jne TryAMD\n\t" |
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94 "cmpl $0x6c65746e, %%ecx\n" |
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95 "jne TryAMD\n\t" "jmp Intel\n\t" |
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96 /* Check for AMD */ |
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97 "\nTryAMD:\n\t" |
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98 "cmpl $0x68747541, %%ebx\n\t" |
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99 "jne TryCyrix\n\t" |
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100 "cmpl $0x69746e65, %%edx\n\t" |
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101 "jne TryCyrix\n\t" |
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102 "cmpl $0x444d4163, %%ecx\n" |
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103 "jne TryCyrix\n\t" "jmp AMD\n\t" |
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104 /* Check for Cyrix */ |
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105 "\nTryCyrix:\n\t" |
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106 "cmpl $0x69727943, %%ebx\n\t" |
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107 "jne NotSupported2\n\t" |
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108 "cmpl $0x736e4978, %%edx\n\t" |
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109 "jne NotSupported3\n\t" |
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110 "cmpl $0x64616574, %%ecx\n\t" |
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111 "jne NotSupported4\n\t" |
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112 /* Drop through to Cyrix... */ |
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113 /* Cyrix Section */ |
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114 /* See if extended CPUID level 80000001 is supported */ |
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115 /* The value of CPUID/80000001 for the 6x86MX is undefined |
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116 according to the Cyrix CPU Detection Guide (Preliminary |
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117 Rev. 1.01 table 1), so we'll check the value of eax for |
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118 CPUID/0 to see if standard CPUID level 2 is supported. |
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119 According to the table, the only CPU which supports level |
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120 2 is also the only one which supports extended CPUID levels. |
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121 */ |
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122 "cmpl $0x2, %%eax\n\t" "jne MMXtest\n\t" /* Use standard CPUID instead */ |
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123 /* Extended CPUID supported (in theory), so get extended |
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124 features */ |
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125 "movl $0x80000001, %%eax\n\t" "cpuid\n\t" "testl $0x00800000, %%eax\n\t" /* Test for MMX */ |
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126 "jz NotSupported5\n\t" /* MMX not supported */ |
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127 "testl $0x01000000, %%eax\n\t" /* Test for Ext'd MMX */ |
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128 "jnz EMMXSupported\n\t" "movl $1, %0:\n\n\t" /* MMX Supported */ |
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129 "jmp Return\n\n" "EMMXSupported:\n\t" "movl $3, %0:\n\n\t" /* EMMX and MMX Supported */ |
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130 "jmp Return\n\t" |
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131 /* AMD Section */ |
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132 "AMD:\n\t" |
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133 /* See if extended CPUID is supported */ |
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134 "movl $0x80000000, %%eax\n\t" "cpuid\n\t" "cmpl $0x80000000, %%eax\n\t" "jl MMXtest\n\t" /* Use standard CPUID instead */ |
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135 /* Extended CPUID supported, so get extended features */ |
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136 "movl $0x80000001, %%eax\n\t" "cpuid\n\t" "testl $0x00800000, %%edx\n\t" /* Test for MMX */ |
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137 "jz NotSupported6\n\t" /* MMX not supported */ |
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138 "testl $0x80000000, %%edx\n\t" /* Test for 3DNow! */ |
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139 "jnz ThreeDNowSupported\n\t" "movl $1, %0:\n\n\t" /* MMX Supported */ |
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140 "jmp Return\n\n" "ThreeDNowSupported:\n\t" "movl $5, %0:\n\n\t" /* 3DNow! and MMX Supported */ |
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141 "jmp Return\n\t" |
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142 /* Intel Section */ |
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143 "Intel:\n\t" |
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144 /* Check for MMX */ |
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145 "MMXtest:\n\t" "movl $1, %%eax\n\t" "cpuid\n\t" "testl $0x00800000, %%edx\n\t" /* Test for MMX */ |
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146 "jz NotSupported7\n\t" /* MMX Not supported */ |
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147 "movl $1, %0:\n\n\t" /* MMX Supported */ |
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148 "jmp Return\n\t" |
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149 /* Nothing supported */ |
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150 "\nNotSupported1:\n\t" "#movl $101, %0:\n\n\t" "\nNotSupported2:\n\t" "#movl $102, %0:\n\n\t" "\nNotSupported3:\n\t" "#movl $103, %0:\n\n\t" "\nNotSupported4:\n\t" "#movl $104, %0:\n\n\t" "\nNotSupported5:\n\t" "#movl $105, %0:\n\n\t" "\nNotSupported6:\n\t" "#movl $106, %0:\n\n\t" "\nNotSupported7:\n\t" "#movl $107, %0:\n\n\t" "movl $0, %0:\n\n\t" "Return:\n\t":"=a"(rval): /* no input */ |
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151 :"eax", "ebx", "ecx", "edx"); |
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152 |
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153 /* Return */ |
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154 return (rval); |
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155 } |
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156 |
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157 /* Function to test if mmx instructions are supported... |
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158 */ |
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159 inline extern int |
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160 mmx_ok(void) |
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161 { |
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162 /* Returns 1 if MMX instructions are supported, 0 otherwise */ |
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163 return (mm_support() & 0x1); |
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164 } |
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165 #endif |
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166 |
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167 /* Helper functions for the instruction macros that follow... |
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168 (note that memory-to-register, m2r, instructions are nearly |
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169 as efficient as register-to-register, r2r, instructions; |
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170 however, memory-to-memory instructions are really simulated |
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171 as a convenience, and are only 1/3 as efficient) |
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172 */ |
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173 #ifdef MMX_TRACE |
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174 |
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175 /* Include the stuff for printing a trace to stderr... |
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176 */ |
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177 |
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178 #define mmx_i2r(op, imm, reg) \ |
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179 { \ |
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180 mmx_t mmx_trace; \ |
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181 mmx_trace.uq = (imm); \ |
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182 printf(#op "_i2r(" #imm "=0x%08x%08x, ", \ |
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183 mmx_trace.d[1], mmx_trace.d[0]); \ |
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184 __asm__ __volatile__ ("movq %%" #reg ", %0" \ |
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185 : "=X" (mmx_trace) \ |
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186 : /* nothing */ ); \ |
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187 printf(#reg "=0x%08x%08x) => ", \ |
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188 mmx_trace.d[1], mmx_trace.d[0]); \ |
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189 __asm__ __volatile__ (#op " %0, %%" #reg \ |
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190 : /* nothing */ \ |
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191 : "X" (imm)); \ |
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192 __asm__ __volatile__ ("movq %%" #reg ", %0" \ |
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193 : "=X" (mmx_trace) \ |
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194 : /* nothing */ ); \ |
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195 printf(#reg "=0x%08x%08x\n", \ |
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196 mmx_trace.d[1], mmx_trace.d[0]); \ |
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197 } |
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198 |
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199 #define mmx_m2r(op, mem, reg) \ |
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200 { \ |
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201 mmx_t mmx_trace; \ |
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202 mmx_trace = (mem); \ |
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203 printf(#op "_m2r(" #mem "=0x%08x%08x, ", \ |
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204 mmx_trace.d[1], mmx_trace.d[0]); \ |
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205 __asm__ __volatile__ ("movq %%" #reg ", %0" \ |
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206 : "=X" (mmx_trace) \ |
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207 : /* nothing */ ); \ |
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208 printf(#reg "=0x%08x%08x) => ", \ |
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209 mmx_trace.d[1], mmx_trace.d[0]); \ |
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210 __asm__ __volatile__ (#op " %0, %%" #reg \ |
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211 : /* nothing */ \ |
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212 : "X" (mem)); \ |
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213 __asm__ __volatile__ ("movq %%" #reg ", %0" \ |
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214 : "=X" (mmx_trace) \ |
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215 : /* nothing */ ); \ |
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216 printf(#reg "=0x%08x%08x\n", \ |
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217 mmx_trace.d[1], mmx_trace.d[0]); \ |
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218 } |
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219 |
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220 #define mmx_r2m(op, reg, mem) \ |
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221 { \ |
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222 mmx_t mmx_trace; \ |
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223 __asm__ __volatile__ ("movq %%" #reg ", %0" \ |
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224 : "=X" (mmx_trace) \ |
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225 : /* nothing */ ); \ |
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226 printf(#op "_r2m(" #reg "=0x%08x%08x, ", \ |
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227 mmx_trace.d[1], mmx_trace.d[0]); \ |
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228 mmx_trace = (mem); \ |
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229 printf(#mem "=0x%08x%08x) => ", \ |
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230 mmx_trace.d[1], mmx_trace.d[0]); \ |
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231 __asm__ __volatile__ (#op " %%" #reg ", %0" \ |
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232 : "=X" (mem) \ |
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233 : /* nothing */ ); \ |
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234 mmx_trace = (mem); \ |
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235 printf(#mem "=0x%08x%08x\n", \ |
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236 mmx_trace.d[1], mmx_trace.d[0]); \ |
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237 } |
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238 |
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239 #define mmx_r2r(op, regs, regd) \ |
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240 { \ |
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241 mmx_t mmx_trace; \ |
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242 __asm__ __volatile__ ("movq %%" #regs ", %0" \ |
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243 : "=X" (mmx_trace) \ |
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244 : /* nothing */ ); \ |
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245 printf(#op "_r2r(" #regs "=0x%08x%08x, ", \ |
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246 mmx_trace.d[1], mmx_trace.d[0]); \ |
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247 __asm__ __volatile__ ("movq %%" #regd ", %0" \ |
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248 : "=X" (mmx_trace) \ |
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249 : /* nothing */ ); \ |
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250 printf(#regd "=0x%08x%08x) => ", \ |
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251 mmx_trace.d[1], mmx_trace.d[0]); \ |
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252 __asm__ __volatile__ (#op " %" #regs ", %" #regd); \ |
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253 __asm__ __volatile__ ("movq %%" #regd ", %0" \ |
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254 : "=X" (mmx_trace) \ |
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255 : /* nothing */ ); \ |
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256 printf(#regd "=0x%08x%08x\n", \ |
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257 mmx_trace.d[1], mmx_trace.d[0]); \ |
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258 } |
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259 |
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260 #define mmx_m2m(op, mems, memd) \ |
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261 { \ |
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262 mmx_t mmx_trace; \ |
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263 mmx_trace = (mems); \ |
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264 printf(#op "_m2m(" #mems "=0x%08x%08x, ", \ |
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265 mmx_trace.d[1], mmx_trace.d[0]); \ |
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266 mmx_trace = (memd); \ |
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267 printf(#memd "=0x%08x%08x) => ", \ |
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268 mmx_trace.d[1], mmx_trace.d[0]); \ |
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269 __asm__ __volatile__ ("movq %0, %%mm0\n\t" \ |
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270 #op " %1, %%mm0\n\t" \ |
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271 "movq %%mm0, %0" \ |
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272 : "=X" (memd) \ |
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273 : "X" (mems)); \ |
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274 mmx_trace = (memd); \ |
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275 printf(#memd "=0x%08x%08x\n", \ |
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276 mmx_trace.d[1], mmx_trace.d[0]); \ |
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277 } |
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278 |
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279 #else |
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280 |
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281 /* These macros are a lot simpler without the tracing... |
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282 */ |
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283 |
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284 #define mmx_i2r(op, imm, reg) \ |
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285 __asm__ __volatile__ (#op " %0, %%" #reg \ |
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286 : /* nothing */ \ |
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287 : "X" (imm) ) |
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288 |
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289 #define mmx_m2r(op, mem, reg) \ |
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290 __asm__ __volatile__ (#op " %0, %%" #reg \ |
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291 : /* nothing */ \ |
738
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292 : "m" (mem)) |
689
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293 |
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294 #define mmx_r2m(op, reg, mem) \ |
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295 __asm__ __volatile__ (#op " %%" #reg ", %0" \ |
5130 | 296 : "=m" (mem) \ |
689
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297 : /* nothing */ ) |
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298 |
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299 #define mmx_r2r(op, regs, regd) \ |
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300 __asm__ __volatile__ (#op " %" #regs ", %" #regd) |
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301 |
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302 #define mmx_m2m(op, mems, memd) \ |
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303 __asm__ __volatile__ ("movq %0, %%mm0\n\t" \ |
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304 #op " %1, %%mm0\n\t" \ |
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305 "movq %%mm0, %0" \ |
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306 : "=X" (memd) \ |
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307 : "X" (mems)) |
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308 |
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309 #endif |
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310 |
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311 |
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312 /* 1x64 MOVe Quadword |
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313 (this is both a load and a store... |
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314 in fact, it is the only way to store) |
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315 */ |
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316 #define movq_m2r(var, reg) mmx_m2r(movq, var, reg) |
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317 #define movq_r2m(reg, var) mmx_r2m(movq, reg, var) |
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318 #define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd) |
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319 #define movq(vars, vard) \ |
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320 __asm__ __volatile__ ("movq %1, %%mm0\n\t" \ |
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321 "movq %%mm0, %0" \ |
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322 : "=X" (vard) \ |
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323 : "X" (vars)) |
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324 |
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325 |
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326 /* 1x32 MOVe Doubleword |
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327 (like movq, this is both load and store... |
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328 but is most useful for moving things between |
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329 mmx registers and ordinary registers) |
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330 */ |
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331 #define movd_m2r(var, reg) mmx_m2r(movd, var, reg) |
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332 #define movd_r2m(reg, var) mmx_r2m(movd, reg, var) |
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333 #define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd) |
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334 #define movd(vars, vard) \ |
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335 __asm__ __volatile__ ("movd %1, %%mm0\n\t" \ |
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336 "movd %%mm0, %0" \ |
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337 : "=X" (vard) \ |
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338 : "X" (vars)) |
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339 |
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340 |
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341 /* 2x32, 4x16, and 8x8 Parallel ADDs |
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342 */ |
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343 #define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg) |
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344 #define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd) |
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345 #define paddd(vars, vard) mmx_m2m(paddd, vars, vard) |
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346 |
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347 #define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg) |
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348 #define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd) |
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349 #define paddw(vars, vard) mmx_m2m(paddw, vars, vard) |
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350 |
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351 #define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg) |
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352 #define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd) |
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353 #define paddb(vars, vard) mmx_m2m(paddb, vars, vard) |
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354 |
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355 |
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356 /* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic |
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357 */ |
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358 #define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg) |
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359 #define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd) |
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360 #define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard) |
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361 |
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362 #define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg) |
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363 #define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd) |
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364 #define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard) |
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365 |
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366 |
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367 /* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic |
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368 */ |
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369 #define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg) |
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370 #define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd) |
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371 #define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard) |
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372 |
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373 #define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg) |
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374 #define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd) |
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375 #define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard) |
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376 |
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377 |
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378 /* 2x32, 4x16, and 8x8 Parallel SUBs |
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379 */ |
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380 #define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg) |
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381 #define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd) |
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382 #define psubd(vars, vard) mmx_m2m(psubd, vars, vard) |
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383 |
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384 #define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg) |
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385 #define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd) |
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386 #define psubw(vars, vard) mmx_m2m(psubw, vars, vard) |
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387 |
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388 #define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg) |
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389 #define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd) |
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390 #define psubb(vars, vard) mmx_m2m(psubb, vars, vard) |
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391 |
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392 |
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393 /* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic |
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394 */ |
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395 #define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg) |
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396 #define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd) |
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397 #define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard) |
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398 |
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399 #define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg) |
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400 #define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd) |
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401 #define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard) |
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402 |
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403 |
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404 /* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic |
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405 */ |
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406 #define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg) |
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407 #define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd) |
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408 #define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard) |
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409 |
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410 #define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg) |
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411 #define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd) |
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412 #define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard) |
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413 |
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414 |
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415 /* 4x16 Parallel MULs giving Low 4x16 portions of results |
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416 */ |
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417 #define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg) |
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418 #define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd) |
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419 #define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard) |
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420 |
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421 |
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422 /* 4x16 Parallel MULs giving High 4x16 portions of results |
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423 */ |
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424 #define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg) |
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425 #define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd) |
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426 #define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard) |
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427 |
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428 |
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429 /* 4x16->2x32 Parallel Mul-ADD |
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430 (muls like pmullw, then adds adjacent 16-bit fields |
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431 in the multiply result to make the final 2x32 result) |
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432 */ |
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433 #define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg) |
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434 #define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd) |
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435 #define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard) |
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436 |
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437 |
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438 /* 1x64 bitwise AND |
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439 */ |
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440 #ifdef BROKEN_PAND |
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441 #define pand_m2r(var, reg) \ |
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442 { \ |
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443 mmx_m2r(pandn, (mmx_t) -1LL, reg); \ |
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444 mmx_m2r(pandn, var, reg); \ |
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445 } |
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446 #define pand_r2r(regs, regd) \ |
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447 { \ |
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448 mmx_m2r(pandn, (mmx_t) -1LL, regd); \ |
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449 mmx_r2r(pandn, regs, regd) \ |
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450 } |
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451 #define pand(vars, vard) \ |
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452 { \ |
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453 movq_m2r(vard, mm0); \ |
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454 mmx_m2r(pandn, (mmx_t) -1LL, mm0); \ |
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455 mmx_m2r(pandn, vars, mm0); \ |
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456 movq_r2m(mm0, vard); \ |
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457 } |
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458 #else |
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459 #define pand_m2r(var, reg) mmx_m2r(pand, var, reg) |
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460 #define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd) |
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461 #define pand(vars, vard) mmx_m2m(pand, vars, vard) |
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462 #endif |
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463 |
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464 |
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465 /* 1x64 bitwise AND with Not the destination |
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466 */ |
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467 #define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg) |
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468 #define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd) |
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469 #define pandn(vars, vard) mmx_m2m(pandn, vars, vard) |
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470 |
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471 |
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472 /* 1x64 bitwise OR |
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473 */ |
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474 #define por_m2r(var, reg) mmx_m2r(por, var, reg) |
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475 #define por_r2r(regs, regd) mmx_r2r(por, regs, regd) |
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476 #define por(vars, vard) mmx_m2m(por, vars, vard) |
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477 |
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478 |
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479 /* 1x64 bitwise eXclusive OR |
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480 */ |
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481 #define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg) |
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482 #define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd) |
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483 #define pxor(vars, vard) mmx_m2m(pxor, vars, vard) |
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484 |
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485 |
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486 /* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality |
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487 (resulting fields are either 0 or -1) |
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488 */ |
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489 #define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg) |
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490 #define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd) |
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491 #define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard) |
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492 |
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493 #define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg) |
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494 #define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd) |
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495 #define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard) |
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496 |
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497 #define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg) |
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498 #define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd) |
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499 #define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard) |
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500 |
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501 |
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502 /* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than |
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503 (resulting fields are either 0 or -1) |
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504 */ |
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505 #define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg) |
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506 #define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd) |
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507 #define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard) |
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508 |
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509 #define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg) |
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510 #define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd) |
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511 #define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard) |
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512 |
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513 #define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg) |
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514 #define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd) |
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515 #define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard) |
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516 |
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517 |
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518 /* 1x64, 2x32, and 4x16 Parallel Shift Left Logical |
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519 */ |
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520 #define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg) |
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521 #define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg) |
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522 #define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd) |
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523 #define psllq(vars, vard) mmx_m2m(psllq, vars, vard) |
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524 |
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525 #define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, reg) |
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526 #define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg) |
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527 #define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd) |
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528 #define pslld(vars, vard) mmx_m2m(pslld, vars, vard) |
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529 |
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530 #define psllw_i2r(imm, reg) mmx_i2r(psllw, imm, reg) |
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531 #define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg) |
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532 #define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd) |
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533 #define psllw(vars, vard) mmx_m2m(psllw, vars, vard) |
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534 |
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535 |
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536 /* 1x64, 2x32, and 4x16 Parallel Shift Right Logical |
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537 */ |
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538 #define psrlq_i2r(imm, reg) mmx_i2r(psrlq, imm, reg) |
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539 #define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg) |
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540 #define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd) |
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541 #define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard) |
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542 |
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543 #define psrld_i2r(imm, reg) mmx_i2r(psrld, imm, reg) |
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544 #define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg) |
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545 #define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd) |
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546 #define psrld(vars, vard) mmx_m2m(psrld, vars, vard) |
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547 |
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548 #define psrlw_i2r(imm, reg) mmx_i2r(psrlw, imm, reg) |
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549 #define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg) |
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550 #define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd) |
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551 #define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard) |
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552 |
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553 |
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554 /* 2x32 and 4x16 Parallel Shift Right Arithmetic |
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555 */ |
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556 #define psrad_i2r(imm, reg) mmx_i2r(psrad, imm, reg) |
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557 #define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg) |
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558 #define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd) |
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559 #define psrad(vars, vard) mmx_m2m(psrad, vars, vard) |
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560 |
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561 #define psraw_i2r(imm, reg) mmx_i2r(psraw, imm, reg) |
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562 #define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg) |
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563 #define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd) |
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564 #define psraw(vars, vard) mmx_m2m(psraw, vars, vard) |
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565 |
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566 |
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567 /* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate |
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568 (packs source and dest fields into dest in that order) |
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569 */ |
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570 #define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg) |
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571 #define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd) |
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572 #define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard) |
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573 |
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574 #define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg) |
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575 #define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd) |
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576 #define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard) |
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577 |
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578 |
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579 /* 4x16->8x8 PACK and Unsigned Saturate |
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580 (packs source and dest fields into dest in that order) |
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581 */ |
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582 #define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg) |
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583 #define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd) |
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584 #define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard) |
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585 |
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586 |
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587 /* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low |
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588 (interleaves low half of dest with low half of source |
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589 as padding in each result field) |
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590 */ |
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591 #define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg) |
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592 #define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd) |
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593 #define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard) |
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594 |
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595 #define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg) |
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596 #define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd) |
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597 #define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard) |
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598 |
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599 #define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg) |
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600 #define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd) |
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601 #define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard) |
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602 |
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603 |
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604 /* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High |
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605 (interleaves high half of dest with high half of source |
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606 as padding in each result field) |
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607 */ |
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608 #define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg) |
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609 #define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd) |
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610 #define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard) |
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611 |
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612 #define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg) |
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613 #define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd) |
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614 #define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard) |
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615 |
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616 #define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg) |
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617 #define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd) |
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618 #define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard) |
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619 |
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620 |
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621 /* Empty MMx State |
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622 (used to clean-up when going from mmx to float use |
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623 of the registers that are shared by both; note that |
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624 there is no float-to-mmx operation needed, because |
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625 only the float tag word info is corruptible) |
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626 */ |
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627 #ifdef MMX_TRACE |
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628 |
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629 #define emms() \ |
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630 { \ |
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631 printf("emms()\n"); \ |
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632 __asm__ __volatile__ ("emms"); \ |
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633 } |
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634 |
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635 #else |
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636 |
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637 #define emms() __asm__ __volatile__ ("emms") |
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638 |
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639 #endif |
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640 |
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641 #endif |
1895
c121d94672cb
SDL 1.2 is moving to a branch, and SDL 1.3 is becoming the head.
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642 /* vi: set ts=4 sw=4 expandtab: */ |