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annotate src/video/fbcon/riva_mmio.h @ 2893:e67f3f3bf221

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Turn on line antialiasing (requires blending to be enabled)
author Sam Lantinga <slouken@libsdl.org>
date Sat, 20 Dec 2008 18:40:30 +0000
parents c121d94672cb
children
rev   line source
133
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1 /***************************************************************************\
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2 |* *|
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3 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
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4 |* *|
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5 |* NOTICE TO USER: The source code is copyrighted under U.S. and *|
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6 |* international laws. Users and possessors of this source code are *|
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7 |* hereby granted a nonexclusive, royalty-free copyright license to *|
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8 |* use this code in individual and commercial software. *|
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9 |* *|
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10 |* Any use of this source code must include, in the user documenta- *|
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11 |* tion and internal comments to the code, notices to the end user *|
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12 |* as follows: *|
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13 |* *|
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14 |* Copyright 1993-1999 NVIDIA, Corporation. All rights reserved. *|
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15 |* *|
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16 |* NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY *|
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17 |* OF THIS SOURCE CODE FOR ANY PURPOSE. IT IS PROVIDED "AS IS" *|
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18 |* WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND. NVIDIA, CORPOR- *|
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19 |* ATION DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOURCE CODE, *|
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20 |* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE- *|
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21 |* MENT, AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL *|
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22 |* NVIDIA, CORPORATION BE LIABLE FOR ANY SPECIAL, INDIRECT, INCI- *|
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23 |* DENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY DAMAGES WHATSOEVER RE- *|
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24 |* SULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION *|
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25 |* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF *|
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26 |* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE. *|
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27 |* *|
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28 |* U.S. Government End Users. This source code is a "commercial *|
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29 |* item," as that term is defined at 48 C.F.R. 2.101 (OCT 1995), *|
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30 |* consisting of "commercial computer software" and "commercial *|
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31 |* computer software documentation," as such terms are used in *|
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32 |* 48 C.F.R. 12.212 (SEPT 1995) and is provided to the U.S. Govern- *|
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33 |* ment only as a commercial end item. Consistent with 48 C.F.R. *|
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34 |* 12.212 and 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), *|
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35 |* all U.S. Government End Users acquire the source code with only *|
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36 |* those rights set forth herein. *|
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37 |* *|
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38 \***************************************************************************/
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39
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40 #ifndef __RIVA_HW_H__
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41 #define __RIVA_HW_H__
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42 #define RIVA_SW_VERSION 0x00010003
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43
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44 /*
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45 * Typedefs to force certain sized values.
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46 */
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47 typedef Uint8 U008;
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48 typedef Uint16 U016;
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49 typedef Uint32 U032;
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50
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51 /*
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52 * HW access macros.
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53 */
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54 #define NV_WR08(p,i,d) (((U008 *)(p))[i]=(d))
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55 #define NV_RD08(p,i) (((U008 *)(p))[i])
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56 #define NV_WR16(p,i,d) (((U016 *)(p))[(i)/2]=(d))
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57 #define NV_RD16(p,i) (((U016 *)(p))[(i)/2])
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58 #define NV_WR32(p,i,d) (((U032 *)(p))[(i)/4]=(d))
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59 #define NV_RD32(p,i) (((U032 *)(p))[(i)/4])
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60 #define VGA_WR08(p,i,d) NV_WR08(p,i,d)
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61 #define VGA_RD08(p,i) NV_RD08(p,i)
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62
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63 /*
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64 * Define supported architectures.
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65 */
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66 #define NV_ARCH_03 0x03
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67 #define NV_ARCH_04 0x04
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68 #define NV_ARCH_10 0x10
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69 /***************************************************************************\
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70 * *
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71 * FIFO registers. *
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72 * *
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73 \***************************************************************************/
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74
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75 /*
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76 * Raster OPeration. Windows style ROP3.
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77 */
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78 typedef volatile struct
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79 {
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80 U032 reserved00[4];
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81 U016 FifoFree;
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82 U016 Nop;
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83 U032 reserved01[0x0BB];
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84 U032 Rop3;
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85 } RivaRop;
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86 /*
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87 * 8X8 Monochrome pattern.
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88 */
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89 typedef volatile struct
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90 {
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91 U032 reserved00[4];
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92 U016 FifoFree;
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93 U016 Nop;
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94 U032 reserved01[0x0BD];
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95 U032 Shape;
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96 U032 reserved03[0x001];
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97 U032 Color0;
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98 U032 Color1;
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99 U032 Monochrome[2];
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100 } RivaPattern;
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101 /*
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102 * Scissor clip rectangle.
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103 */
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104 typedef volatile struct
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105 {
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106 U032 reserved00[4];
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107 U016 FifoFree;
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108 U016 Nop;
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109 U032 reserved01[0x0BB];
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110 U032 TopLeft;
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111 U032 WidthHeight;
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112 } RivaClip;
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113 /*
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114 * 2D filled rectangle.
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115 */
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116 typedef volatile struct
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117 {
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118 U032 reserved00[4];
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119 U016 FifoFree;
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120 U016 Nop[1];
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121 U032 reserved01[0x0BC];
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122 U032 Color;
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123 U032 reserved03[0x03E];
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124 U032 TopLeft;
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125 U032 WidthHeight;
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126 } RivaRectangle;
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127 /*
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128 * 2D screen-screen BLT.
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129 */
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130 typedef volatile struct
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131 {
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132 U032 reserved00[4];
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133 U016 FifoFree;
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134 U016 Nop;
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135 U032 reserved01[0x0BB];
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136 U032 TopLeftSrc;
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137 U032 TopLeftDst;
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138 U032 WidthHeight;
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139 } RivaScreenBlt;
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140 /*
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141 * 2D pixel BLT.
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142 */
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143 typedef volatile struct
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144 {
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145 U032 reserved00[4];
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146 U016 FifoFree;
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147 U016 Nop[1];
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148 U032 reserved01[0x0BC];
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149 U032 TopLeft;
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150 U032 WidthHeight;
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151 U032 WidthHeightIn;
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152 U032 reserved02[0x03C];
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153 U032 Pixels;
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154 } RivaPixmap;
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155 /*
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156 * Filled rectangle combined with monochrome expand. Useful for glyphs.
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157 */
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158 typedef volatile struct
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159 {
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160 U032 reserved00[4];
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161 U016 FifoFree;
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162 U016 Nop;
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163 U032 reserved01[0x0BB];
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164 U032 reserved03[(0x040) - 1];
133
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165 U032 Color1A;
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166 struct
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167 {
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168 U032 TopLeft;
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169 U032 WidthHeight;
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170 } UnclippedRectangle[64];
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171 U032 reserved04[(0x080) - 3];
133
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172 struct
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173 {
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174 U032 TopLeft;
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175 U032 BottomRight;
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176 } ClipB;
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177 U032 Color1B;
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178 struct
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179 {
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180 U032 TopLeft;
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181 U032 BottomRight;
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182 } ClippedRectangle[64];
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183 U032 reserved05[(0x080) - 5];
133
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184 struct
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185 {
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186 U032 TopLeft;
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187 U032 BottomRight;
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188 } ClipC;
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189 U032 Color1C;
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190 U032 WidthHeightC;
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191 U032 PointC;
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192 U032 MonochromeData1C;
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193 U032 reserved06[(0x080) + 121];
133
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194 struct
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195 {
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196 U032 TopLeft;
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197 U032 BottomRight;
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198 } ClipD;
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199 U032 Color1D;
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200 U032 WidthHeightInD;
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201 U032 WidthHeightOutD;
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202 U032 PointD;
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203 U032 MonochromeData1D;
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204 U032 reserved07[(0x080) + 120];
133
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205 struct
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206 {
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207 U032 TopLeft;
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208 U032 BottomRight;
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209 } ClipE;
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210 U032 Color0E;
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211 U032 Color1E;
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212 U032 WidthHeightInE;
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213 U032 WidthHeightOutE;
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214 U032 PointE;
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215 U032 MonochromeData01E;
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216 } RivaBitmap;
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217 /*
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218 * 3D textured, Z buffered triangle.
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219 */
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220 typedef volatile struct
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221 {
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222 U032 reserved00[4];
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223 U016 FifoFree;
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224 U016 Nop;
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225 U032 reserved01[0x0BC];
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226 U032 TextureOffset;
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227 U032 TextureFormat;
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228 U032 TextureFilter;
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229 U032 FogColor;
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230 /* This is a problem on LynxOS */
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231 #ifdef Control
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232 #undef Control
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233 #endif
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234 U032 Control;
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235 U032 AlphaTest;
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236 U032 reserved02[0x339];
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237 U032 FogAndIndex;
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238 U032 Color;
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239 float ScreenX;
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240 float ScreenY;
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241 float ScreenZ;
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242 float EyeM;
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243 float TextureS;
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244 float TextureT;
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245 } RivaTexturedTriangle03;
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246 typedef volatile struct
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247 {
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248 U032 reserved00[4];
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249 U016 FifoFree;
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250 U016 Nop;
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251 U032 reserved01[0x0BB];
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252 U032 ColorKey;
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253 U032 TextureOffset;
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254 U032 TextureFormat;
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255 U032 TextureFilter;
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256 U032 Blend;
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257 /* This is a problem on LynxOS */
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258 #ifdef Control
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259 #undef Control
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260 #endif
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261 U032 Control;
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262 U032 FogColor;
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263 U032 reserved02[0x39];
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264 struct
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265 {
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266 float ScreenX;
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267 float ScreenY;
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268 float ScreenZ;
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269 float EyeM;
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270 U032 Color;
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271 U032 Specular;
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272 float TextureS;
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273 float TextureT;
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274 } Vertex[16];
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275 U032 DrawTriangle3D;
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276 } RivaTexturedTriangle05;
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277 /*
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278 * 2D line.
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279 */
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280 typedef volatile struct
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281 {
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282 U032 reserved00[4];
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283 U016 FifoFree;
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284 U016 Nop[1];
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285 U032 reserved01[0x0BC];
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286 U032 Color; /* source color 0304-0307 */
133
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287 U032 Reserved02[0x03e];
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288 struct
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289 { /* start aliased methods in array 0400- */
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290 U032 point0; /* y_x S16_S16 in pixels 0- 3 */
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291 U032 point1; /* y_x S16_S16 in pixels 4- 7 */
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292 } Lin[16]; /* end of aliased methods in array -047f */
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293 struct
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294 { /* start aliased methods in array 0480- */
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295 U032 point0X; /* in pixels, 0 at left 0- 3 */
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296 U032 point0Y; /* in pixels, 0 at top 4- 7 */
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297 U032 point1X; /* in pixels, 0 at left 8- b */
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298 U032 point1Y; /* in pixels, 0 at top c- f */
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299 } Lin32[8]; /* end of aliased methods in array -04ff */
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300 U032 PolyLin[32]; /* y_x S16_S16 in pixels 0500-057f */
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301 struct
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302 { /* start aliased methods in array 0580- */
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303 U032 x; /* in pixels, 0 at left 0- 3 */
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304 U032 y; /* in pixels, 0 at top 4- 7 */
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305 } PolyLin32[16]; /* end of aliased methods in array -05ff */
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306 struct
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307 { /* start aliased methods in array 0600- */
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308 U032 color; /* source color 0- 3 */
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309 U032 point; /* y_x S16_S16 in pixels 4- 7 */
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310 } ColorPolyLin[16]; /* end of aliased methods in array -067f */
133
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311 } RivaLine;
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312 /*
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313 * 2D/3D surfaces
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314 */
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315 typedef volatile struct
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316 {
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317 U032 reserved00[4];
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318 U016 FifoFree;
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319 U016 Nop;
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320 U032 reserved01[0x0BE];
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321 U032 Offset;
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322 } RivaSurface;
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323 typedef volatile struct
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324 {
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325 U032 reserved00[4];
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326 U016 FifoFree;
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327 U016 Nop;
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328 U032 reserved01[0x0BD];
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329 U032 Pitch;
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330 U032 RenderBufferOffset;
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331 U032 ZBufferOffset;
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332 } RivaSurface3D;
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333
133
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334 /***************************************************************************\
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335 * *
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336 * Virtualized RIVA H/W interface. *
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337 * *
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338 \***************************************************************************/
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339
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340 struct _riva_hw_inst;
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341 struct _riva_hw_state;
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342 /*
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343 * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
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344 */
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345 typedef struct _riva_hw_inst
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346 {
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347 /*
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348 * Chip specific settings.
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349 */
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350 U032 Architecture;
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351 U032 Version;
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352 U032 CrystalFreqKHz;
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353 U032 RamAmountKBytes;
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354 U032 MaxVClockFreqKHz;
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355 U032 RamBandwidthKBytesPerSec;
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356 U032 EnableIRQ;
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357 U032 IO;
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358 U032 VBlankBit;
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359 U032 FifoFreeCount;
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360 U032 FifoEmptyCount;
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361 /*
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362 * Non-FIFO registers.
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363 */
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364 volatile U032 *PCRTC;
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365 volatile U032 *PRAMDAC;
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366 volatile U032 *PFB;
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367 volatile U032 *PFIFO;
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368 volatile U032 *PGRAPH;
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369 volatile U032 *PEXTDEV;
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370 volatile U032 *PTIMER;
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371 volatile U032 *PMC;
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372 volatile U032 *PRAMIN;
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373 volatile U032 *FIFO;
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374 volatile U032 *CURSOR;
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375 volatile U032 *CURSORPOS;
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376 volatile U032 *VBLANKENABLE;
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377 volatile U032 *VBLANK;
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378 volatile U008 *PCIO;
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379 volatile U008 *PVIO;
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380 volatile U008 *PDIO;
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381 /*
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382 * Common chip functions.
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383 */
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384 int (*Busy) (struct _riva_hw_inst *);
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385 void (*CalcStateExt) (struct _riva_hw_inst *, struct _riva_hw_state *,
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386 int, int, int, int, int, int, int, int, int, int,
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387 int, int, int);
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388 void (*LoadStateExt) (struct _riva_hw_inst *, struct _riva_hw_state *);
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389 void (*UnloadStateExt) (struct _riva_hw_inst *, struct _riva_hw_state *);
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390 void (*SetStartAddress) (struct _riva_hw_inst *, U032);
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391 void (*SetSurfaces2D) (struct _riva_hw_inst *, U032, U032);
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392 void (*SetSurfaces3D) (struct _riva_hw_inst *, U032, U032);
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393 int (*ShowHideCursor) (struct _riva_hw_inst *, int);
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394 void (*LockUnlock) (struct _riva_hw_inst *, int);
133
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395 /*
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396 * Current extended mode settings.
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397 */
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398 struct _riva_hw_state *CurrentState;
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399 /*
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400 * FIFO registers.
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401 */
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402 RivaRop *Rop;
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403 RivaPattern *Patt;
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404 RivaClip *Clip;
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405 RivaPixmap *Pixmap;
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406 RivaScreenBlt *Blt;
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407 RivaBitmap *Bitmap;
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408 RivaLine *Line;
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409 RivaTexturedTriangle03 *Tri03;
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410 RivaTexturedTriangle05 *Tri05;
133
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411 } RIVA_HW_INST;
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412 /*
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413 * Extended mode state information.
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414 */
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415 typedef struct _riva_hw_state
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416 {
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417 U032 bpp;
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418 U032 width;
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419 U032 height;
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420 U032 repaint0;
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421 U032 repaint1;
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422 U032 screen;
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423 U032 pixel;
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424 U032 horiz;
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425 U032 arbitration0;
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426 U032 arbitration1;
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427 U032 vpll;
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428 U032 pllsel;
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429 U032 general;
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430 U032 config;
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431 U032 cursor0;
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432 U032 cursor1;
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433 U032 cursor2;
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434 U032 offset0;
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435 U032 offset1;
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436 U032 offset2;
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437 U032 offset3;
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438 U032 pitch0;
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439 U032 pitch1;
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440 U032 pitch2;
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441 U032 pitch3;
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442 } RIVA_HW_STATE;
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443
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444 /*
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445 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
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446 */
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447
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448 #define RIVA_FIFO_FREE(hwptr,cnt) \
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449 { \
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450 while (FifoFreeCount < (cnt)) \
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451 FifoFreeCount = hwptr->FifoFree >> 2; \
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452 FifoFreeCount -= (cnt); \
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453 }
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454 #endif /* __RIVA_HW_H__ */
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c121d94672cb SDL 1.2 is moving to a branch, and SDL 1.3 is becoming the head.
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455 /* vi: set ts=4 sw=4 expandtab: */