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2 /*
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3 * MGA Millennium (MGA2064W) functions
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4 * MGA Mystique (MGA1064SG) functions
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5 *
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6 * Copyright 1996 The XFree86 Project, Inc.
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7 *
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8 * Authors
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9 * Dirk Hohndel
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10 * hohndel@XFree86.Org
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11 * David Dawes
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12 * dawes@XFree86.Org
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13 * Contributors:
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14 * Guy DESBIEF, Aix-en-provence, France
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15 * g.desbief@aix.pacwan.net
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16 * MGA1064SG Mystique register file
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17 */
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18
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19
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20 #ifndef _MGA_REG_H_
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21 #define _MGA_REG_H_
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22
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23 #define MGAREG_DWGCTL 0x1c00
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24 #define MGAREG_MACCESS 0x1c04
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25 /* the following is a mystique only register */
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26 #define MGAREG_MCTLWTST 0x1c08
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27 #define MGAREG_ZORG 0x1c0c
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28
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29 #define MGAREG_PAT0 0x1c10
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30 #define MGAREG_PAT1 0x1c14
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31 #define MGAREG_PLNWT 0x1c1c
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32
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33 #define MGAREG_BCOL 0x1c20
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34 #define MGAREG_FCOL 0x1c24
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35
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36 #define MGAREG_SRC0 0x1c30
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37 #define MGAREG_SRC1 0x1c34
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38 #define MGAREG_SRC2 0x1c38
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39 #define MGAREG_SRC3 0x1c3c
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40
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41 #define MGAREG_XYSTRT 0x1c40
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42 #define MGAREG_XYEND 0x1c44
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43
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44 #define MGAREG_SHIFT 0x1c50
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45 /* the following is a mystique only register */
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46 #define MGAREG_DMAPAD 0x1c54
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47 #define MGAREG_SGN 0x1c58
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48 #define MGAREG_LEN 0x1c5c
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49
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50 #define MGAREG_AR0 0x1c60
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51 #define MGAREG_AR1 0x1c64
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52 #define MGAREG_AR2 0x1c68
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53 #define MGAREG_AR3 0x1c6c
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54 #define MGAREG_AR4 0x1c70
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55 #define MGAREG_AR5 0x1c74
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56 #define MGAREG_AR6 0x1c78
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57
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58 #define MGAREG_CXBNDRY 0x1c80
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59 #define MGAREG_FXBNDRY 0x1c84
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60 #define MGAREG_YDSTLEN 0x1c88
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61 #define MGAREG_PITCH 0x1c8c
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62
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63 #define MGAREG_YDST 0x1c90
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64 #define MGAREG_YDSTORG 0x1c94
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65 #define MGAREG_YTOP 0x1c98
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66 #define MGAREG_YBOT 0x1c9c
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67
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68 #define MGAREG_CXLEFT 0x1ca0
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69 #define MGAREG_CXRIGHT 0x1ca4
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70 #define MGAREG_FXLEFT 0x1ca8
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71 #define MGAREG_FXRIGHT 0x1cac
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72
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73 #define MGAREG_XDST 0x1cb0
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74
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75 #define MGAREG_DR0 0x1cc0
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76 #define MGAREG_DR1 0x1cc4
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77 #define MGAREG_DR2 0x1cc8
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78 #define MGAREG_DR3 0x1ccc
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79
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80 #define MGAREG_DR4 0x1cd0
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81 #define MGAREG_DR5 0x1cd4
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82 #define MGAREG_DR6 0x1cd8
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83 #define MGAREG_DR7 0x1cdc
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84
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85 #define MGAREG_DR8 0x1ce0
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86 #define MGAREG_DR9 0x1ce4
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87 #define MGAREG_DR10 0x1ce8
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88 #define MGAREG_DR11 0x1cec
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89
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90 #define MGAREG_DR12 0x1cf0
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91 #define MGAREG_DR13 0x1cf4
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92 #define MGAREG_DR14 0x1cf8
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93 #define MGAREG_DR15 0x1cfc
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94
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95 #define MGAREG_SRCORG 0x2cb4
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96 #define MGAREG_DSTORG 0x2cb8
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97
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98 /* add or or this to one of the previous "power registers" to start
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99 the drawing engine */
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100
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101 #define MGAREG_EXEC 0x0100
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102
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103 #define MGAREG_FIFOSTATUS 0x1e10
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104 #define MGAREG_STATUS 0x1e14
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105 #define MGAREG_ICLEAR 0x1e18
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106 #define MGAREG_IEN 0x1e1c
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107
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108 #define MGAREG_VCOUNT 0x1e20
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109
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110 #define MGAREG_Reset 0x1e40
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111
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112 #define MGAREG_OPMODE 0x1e54
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113
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114 /* OPMODE register additives */
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115
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116 #define MGAOPM_DMA_GENERAL (0x00 << 2)
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117 #define MGAOPM_DMA_BLIT (0x01 << 2)
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118 #define MGAOPM_DMA_VECTOR (0x10 << 2)
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119
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120 /* DWGCTL register additives */
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121
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122 /* Lines */
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123
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124 #define MGADWG_LINE_OPEN 0x00
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125 #define MGADWG_AUTOLINE_OPEN 0x01
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126 #define MGADWG_LINE_CLOSE 0x02
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127 #define MGADWG_AUTOLINE_CLOSE 0x03
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128
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129 /* Trapezoids */
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130 #define MGADWG_TRAP 0x04
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131 #define MGADWG_TEXTURE_TRAP 0x05
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132
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133 /* BitBlts */
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134
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135 #define MGADWG_BITBLT 0x08
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136 #define MGADWG_FBITBLT 0x0c
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137 #define MGADWG_ILOAD 0x09
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138 #define MGADWG_ILOAD_SCALE 0x0d
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139 #define MGADWG_ILOAD_FILTER 0x0f
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140 #define MGADWG_IDUMP 0x0a
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141
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142 /* atype access to WRAM */
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143
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144 #define MGADWG_RPL ( 0x00 << 4 )
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145 #define MGADWG_RSTR ( 0x01 << 4 )
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146 #define MGADWG_ZI ( 0x03 << 4 )
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147 #define MGADWG_BLK ( 0x04 << 4 )
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148 #define MGADWG_I ( 0x07 << 4 )
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149
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150 /* specifies whether bit blits are linear or xy */
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151 #define MGADWG_LINEAR ( 0x01 << 7 )
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152
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153 /* z drawing mode. use MGADWG_NOZCMP for always */
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154
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155 #define MGADWG_NOZCMP ( 0x00 << 8 )
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156 #define MGADWG_ZE ( 0x02 << 8 )
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157 #define MGADWG_ZNE ( 0x03 << 8 )
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158 #define MGADWG_ZLT ( 0x04 << 8 )
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159 #define MGADWG_ZLTE ( 0x05 << 8 )
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160 #define MGADWG_GT ( 0x06 << 8 )
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161 #define MGADWG_GTE ( 0x07 << 8 )
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162
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163 /* use this to force colour expansion circuitry to do its stuff */
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164
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165 #define MGADWG_SOLID ( 0x01 << 11 )
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166
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167 /* ar register at zero */
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168
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169 #define MGADWG_ARZERO ( 0x01 << 12 )
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170
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171 #define MGADWG_SGNZERO ( 0x01 << 13 )
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172
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173 #define MGADWG_SHIFTZERO ( 0x01 << 14 )
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174
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175 /* See table on 4-43 for bop ALU operations */
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176
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177 /* See table on 4-44 for translucidity masks */
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178
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179 #define MGADWG_BMONOLEF ( 0x00 << 25 )
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180 #define MGADWG_BMONOWF ( 0x04 << 25 )
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181 #define MGADWG_BPLAN ( 0x01 << 25 )
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182
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183 /* note that if bfcol is specified and you're doing a bitblt, it causes
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184 a fbitblt to be performed, so check that you obey the fbitblt rules */
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185
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186 #define MGADWG_BFCOL ( 0x02 << 25 )
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187 #define MGADWG_BUYUV ( 0x0e << 25 )
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188 #define MGADWG_BU32BGR ( 0x03 << 25 )
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189 #define MGADWG_BU32RGB ( 0x07 << 25 )
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190 #define MGADWG_BU24BGR ( 0x0b << 25 )
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191 #define MGADWG_BU24RGB ( 0x0f << 25 )
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192
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193 #define MGADWG_REPLACE 0x000C0000 /* From Linux kernel sources */
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194 #define MGADWG_PATTERN ( 0x01 << 29 )
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195 #define MGADWG_TRANSC ( 0x01 << 30 )
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196 #define MGADWG_NOCLIP ( 0x01 << 31 )
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197 #define MGAREG_MISC_WRITE 0x3c2
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198 #define MGAREG_MISC_READ 0x3cc
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199 #define MGAREG_MISC_IOADSEL (0x1 << 0)
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200 #define MGAREG_MISC_RAMMAPEN (0x1 << 1)
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201 #define MGAREG_MISC_CLK_SEL_VGA25 (0x0 << 2)
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202 #define MGAREG_MISC_CLK_SEL_VGA28 (0x1 << 2)
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203 #define MGAREG_MISC_CLK_SEL_MGA_PIX (0x2 << 2)
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204 #define MGAREG_MISC_CLK_SEL_MGA_MSK (0x3 << 2)
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205 #define MGAREG_MISC_VIDEO_DIS (0x1 << 4)
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206 #define MGAREG_MISC_HIGH_PG_SEL (0x1 << 5)
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207
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208 /* MMIO VGA registers */
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209 #define MGAREG_CRTC_INDEX 0x1fd4
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210 #define MGAREG_CRTC_DATA 0x1fd5
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211 #define MGAREG_CRTCEXT_INDEX 0x1fde
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212 #define MGAREG_CRTCEXT_DATA 0x1fdf
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213
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214
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215 /* MGA bits for registers PCI_OPTION_REG */
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216 #define MGA1064_OPT_SYS_CLK_PCI ( 0x00 << 0 )
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217 #define MGA1064_OPT_SYS_CLK_PLL ( 0x01 << 0 )
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218 #define MGA1064_OPT_SYS_CLK_EXT ( 0x02 << 0 )
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219 #define MGA1064_OPT_SYS_CLK_MSK ( 0x03 << 0 )
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220
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221 #define MGA1064_OPT_SYS_CLK_DIS ( 0x01 << 2 )
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222 #define MGA1064_OPT_G_CLK_DIV_1 ( 0x01 << 3 )
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223 #define MGA1064_OPT_M_CLK_DIV_1 ( 0x01 << 4 )
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224
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225 #define MGA1064_OPT_SYS_PLL_PDN ( 0x01 << 5 )
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226 #define MGA1064_OPT_VGA_ION ( 0x01 << 8 )
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227
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228 /* MGA registers in PCI config space */
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229 #define PCI_MGA_INDEX 0x44
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230 #define PCI_MGA_DATA 0x48
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231 #define PCI_MGA_OPTION2 0x50
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232 #define PCI_MGA_OPTION3 0x54
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233
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234 #define RAMDAC_OFFSET 0x3c00
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235
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236 /* TVP3026 direct registers */
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237
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238 #define TVP3026_INDEX 0x00
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239 #define TVP3026_WADR_PAL 0x00
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240 #define TVP3026_COL_PAL 0x01
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241 #define TVP3026_PIX_RD_MSK 0x02
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242 #define TVP3026_RADR_PAL 0x03
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243 #define TVP3026_CUR_COL_ADDR 0x04
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244 #define TVP3026_CUR_COL_DATA 0x05
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245 #define TVP3026_DATA 0x0a
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246 #define TVP3026_CUR_RAM 0x0b
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247 #define TVP3026_CUR_XLOW 0x0c
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248 #define TVP3026_CUR_XHI 0x0d
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249 #define TVP3026_CUR_YLOW 0x0e
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250 #define TVP3026_CUR_YHI 0x0f
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251
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252 /* TVP3026 indirect registers */
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253
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254 #define TVP3026_SILICON_REV 0x01
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255 #define TVP3026_CURSOR_CTL 0x06
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256 #define TVP3026_LATCH_CTL 0x0f
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257 #define TVP3026_TRUE_COLOR_CTL 0x18
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258 #define TVP3026_MUX_CTL 0x19
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259 #define TVP3026_CLK_SEL 0x1a
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260 #define TVP3026_PAL_PAGE 0x1c
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261 #define TVP3026_GEN_CTL 0x1d
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262 #define TVP3026_MISC_CTL 0x1e
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263 #define TVP3026_GEN_IO_CTL 0x2a
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264 #define TVP3026_GEN_IO_DATA 0x2b
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265 #define TVP3026_PLL_ADDR 0x2c
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266 #define TVP3026_PIX_CLK_DATA 0x2d
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267 #define TVP3026_MEM_CLK_DATA 0x2e
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268 #define TVP3026_LOAD_CLK_DATA 0x2f
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269 #define TVP3026_KEY_RED_LOW 0x32
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270 #define TVP3026_KEY_RED_HI 0x33
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271 #define TVP3026_KEY_GREEN_LOW 0x34
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272 #define TVP3026_KEY_GREEN_HI 0x35
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273 #define TVP3026_KEY_BLUE_LOW 0x36
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274 #define TVP3026_KEY_BLUE_HI 0x37
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275 #define TVP3026_KEY_CTL 0x38
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276 #define TVP3026_MCLK_CTL 0x39
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277 #define TVP3026_SENSE_TEST 0x3a
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278 #define TVP3026_TEST_DATA 0x3b
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279 #define TVP3026_CRC_LSB 0x3c
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280 #define TVP3026_CRC_MSB 0x3d
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281 #define TVP3026_CRC_CTL 0x3e
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282 #define TVP3026_ID 0x3f
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283 #define TVP3026_RESET 0xff
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284
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285
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286 /* MGA1064 DAC Register file */
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287 /* MGA1064 direct registers */
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288
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289 #define MGA1064_INDEX 0x00
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290 #define MGA1064_WADR_PAL 0x00
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291 #define MGA1064_COL_PAL 0x01
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292 #define MGA1064_PIX_RD_MSK 0x02
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293 #define MGA1064_RADR_PAL 0x03
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294 #define MGA1064_DATA 0x0a
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295
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296 #define MGA1064_CUR_XLOW 0x0c
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297 #define MGA1064_CUR_XHI 0x0d
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298 #define MGA1064_CUR_YLOW 0x0e
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299 #define MGA1064_CUR_YHI 0x0f
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300
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301 /* MGA1064 indirect registers */
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302 #define MGA1064_CURSOR_BASE_ADR_LOW 0x04
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303 #define MGA1064_CURSOR_BASE_ADR_HI 0x05
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304 #define MGA1064_CURSOR_CTL 0x06
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305 #define MGA1064_CURSOR_COL0_RED 0x08
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306 #define MGA1064_CURSOR_COL0_GREEN 0x09
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307 #define MGA1064_CURSOR_COL0_BLUE 0x0a
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308
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309 #define MGA1064_CURSOR_COL1_RED 0x0c
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310 #define MGA1064_CURSOR_COL1_GREEN 0x0d
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311 #define MGA1064_CURSOR_COL1_BLUE 0x0e
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312
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313 #define MGA1064_CURSOR_COL2_RED 0x010
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314 #define MGA1064_CURSOR_COL2_GREEN 0x011
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315 #define MGA1064_CURSOR_COL2_BLUE 0x012
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316
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317 #define MGA1064_VREF_CTL 0x018
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318
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319 #define MGA1064_MUL_CTL 0x19
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320 #define MGA1064_MUL_CTL_8bits 0x0
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321 #define MGA1064_MUL_CTL_15bits 0x01
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322 #define MGA1064_MUL_CTL_16bits 0x02
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323 #define MGA1064_MUL_CTL_24bits 0x03
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324 #define MGA1064_MUL_CTL_32bits 0x04
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325 #define MGA1064_MUL_CTL_2G8V16bits 0x05
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326 #define MGA1064_MUL_CTL_G16V16bits 0x06
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327 #define MGA1064_MUL_CTL_32_24bits 0x07
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328
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329 #define MGAGDAC_XVREFCTRL 0x18
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330 #define MGA1064_PIX_CLK_CTL 0x1a
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331 #define MGA1064_PIX_CLK_CTL_CLK_DIS ( 0x01 << 2 )
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332 #define MGA1064_PIX_CLK_CTL_CLK_POW_DOWN ( 0x01 << 3 )
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333 #define MGA1064_PIX_CLK_CTL_SEL_PCI ( 0x00 << 0 )
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334 #define MGA1064_PIX_CLK_CTL_SEL_PLL ( 0x01 << 0 )
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335 #define MGA1064_PIX_CLK_CTL_SEL_EXT ( 0x02 << 0 )
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336 #define MGA1064_PIX_CLK_CTL_SEL_MSK ( 0x03 << 0 )
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337
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338 #define MGA1064_GEN_CTL 0x1d
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339 #define MGA1064_MISC_CTL 0x1e
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340 #define MGA1064_MISC_CTL_DAC_POW_DN ( 0x01 << 0 )
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341 #define MGA1064_MISC_CTL_VGA ( 0x01 << 1 )
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342 #define MGA1064_MISC_CTL_DIS_CON ( 0x03 << 1 )
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343 #define MGA1064_MISC_CTL_MAFC ( 0x02 << 1 )
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344 #define MGA1064_MISC_CTL_VGA8 ( 0x01 << 3 )
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345 #define MGA1064_MISC_CTL_DAC_RAM_CS ( 0x01 << 4 )
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346
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347 #define MGA1064_GEN_IO_CTL 0x2a
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348 #define MGA1064_GEN_IO_DATA 0x2b
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349 #define MGA1064_SYS_PLL_M 0x2c
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350 #define MGA1064_SYS_PLL_N 0x2d
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351 #define MGA1064_SYS_PLL_P 0x2e
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352 #define MGA1064_SYS_PLL_STAT 0x2f
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353 #define MGA1064_ZOOM_CTL 0x38
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354 #define MGA1064_SENSE_TST 0x3a
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355
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356 #define MGA1064_CRC_LSB 0x3c
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357 #define MGA1064_CRC_MSB 0x3d
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358 #define MGA1064_CRC_CTL 0x3e
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359 #define MGA1064_COL_KEY_MSK_LSB 0x40
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360 #define MGA1064_COL_KEY_MSK_MSB 0x41
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361 #define MGA1064_COL_KEY_LSB 0x42
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362 #define MGA1064_COL_KEY_MSB 0x43
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363 #define MGA1064_PIX_PLLA_M 0x44
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364 #define MGA1064_PIX_PLLA_N 0x45
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365 #define MGA1064_PIX_PLLA_P 0x46
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366 #define MGA1064_PIX_PLLB_M 0x48
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367 #define MGA1064_PIX_PLLB_N 0x49
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368 #define MGA1064_PIX_PLLB_P 0x4a
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369 #define MGA1064_PIX_PLLC_M 0x4c
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370 #define MGA1064_PIX_PLLC_N 0x4d
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371 #define MGA1064_PIX_PLLC_P 0x4e
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372
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373 #define MGA1064_PIX_PLL_STAT 0x4f
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374
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375 #endif
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376
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