from target.arminstructions import Orr, Lsl, Str2, Ldr2, Ldr3
from target.arminstructions import B, Bl, Bgt, Blt, Beq, Bne
from target.arminstructions import Mov2, Mov3
from target.arminstructions import Add, Sub, Cmp, Sub2, Add2, Mul

%%

%terminal ADDI32 SUBI32 ORI32 SHLI32
%terminal CONSTI32 MEMI32 REGI32 CALL

%%

reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add, dst=[d], src=[$1, $2]); return d .)
reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$1, $2]); return d .)
reg: ORI32(reg, reg)  2 (. d = self.newTmp(); self.emit(Orr, dst=[d], src=[$1, $2]); return d .)
reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Lsl, dst=[d], src=[$1, $2]); return d .)
reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Mul, dst=[d], src=[$1, $2]); return d .)

reg: CONSTI32         3 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$$.value]); return d .)
reg: MEMI32(reg)      4 (. d = self.newTmp(); self.emit(Ldr2, dst=[d], src=[$1]); return d .)
reg: REGI32           1 (. pass .)
reg: CALL             1 (. pass .)