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comparison python/target/arm.brg @ 322:44f336460c2a

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Half of use of burg spec for arm
author Windel Bouwman
date Mon, 27 Jan 2014 19:58:07 +0100
parents
children e9fe6988497c
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321:8c569fbe60e4 322:44f336460c2a
1
2 from target.arminstructions import Orr, Lsl, Str2, Ldr2, Ldr3
3 from target.arminstructions import B, Bl, Bgt, Blt, Beq, Bne
4 from target.arminstructions import Mov2, Mov3
5 from target.arminstructions import Add, Sub, Cmp, Sub2, Add2, Mul
6
7 %%
8
9 %terminal ADDI32 SUBI32 ORI32 SHLI32
10 %terminal CONSTI32 MEMI32 REGI32 CALL
11
12 %%
13
14 reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add, dst=[d], src=[$1, $2]); return d .)
15 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$1, $2]); return d .)
16 reg: ORI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Orr, dst=[d], src=[$1, $2]); return d .)
17 reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Lsl, dst=[d], src=[$1, $2]); return d .)
18 reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Mul, dst=[d], src=[$1, $2]); return d .)
19
20 reg: CONSTI32 3 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$$.value]); return d .)
21 reg: MEMI32(reg) 4 (. d = self.newTmp(); self.emit(Ldr2, dst=[d], src=[$1]); return d .)
22 reg: REGI32 1 (. pass .)
23 reg: CALL 1 (. pass .)
24
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