--- a/python/target/arm.brg	Mon Jan 27 19:58:07 2014 +0100
+++ b/python/target/arm.brg	Thu Jan 30 19:03:24 2014 +0100
@@ -1,4 +1,5 @@
 
+from target.basetarget import Label, Comment, Alignment, LabelRef, DebugInfo, Nop
 from target.arminstructions import Orr, Lsl, Str2, Ldr2, Ldr3
 from target.arminstructions import B, Bl, Bgt, Blt, Beq, Bne
 from target.arminstructions import Mov2, Mov3
@@ -6,20 +7,26 @@
 
 %%
 
-%terminal ADDI32 SUBI32 ORI32 SHLI32
+%terminal ADDI32 SUBI32 MULI32
+%terminal ORI32 SHLI32
 %terminal CONSTI32 MEMI32 REGI32 CALL
+%terminal MOVI32
 
 %%
 
+
 reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add, dst=[d], src=[$1, $2]); return d .)
 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$1, $2]); return d .)
-reg: ORI32(reg, reg)  2 (. d = self.newTmp(); self.emit(Orr, dst=[d], src=[$1, $2]); return d .)
-reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Lsl, dst=[d], src=[$1, $2]); return d .)
-reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Mul, dst=[d], src=[$1, $2]); return d .)
+reg: ORI32(reg, reg)  2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Orr, dst=[], src=[d, $2]); return d .)
+reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Lsl, dst=[], src=[d, $2]); return d .)
+reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Mul, dst=[d], src=[$2, d]); return d .)
 
-reg: CONSTI32         3 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$$.value]); return d .)
-reg: MEMI32(reg)      4 (. d = self.newTmp(); self.emit(Ldr2, dst=[d], src=[$1]); return d .)
-reg: REGI32           1 (. pass .)
-reg: CALL             1 (. pass .)
+reg: CONSTI32         3 (. d = self.newTmp(); ln = LabelRef(self.selector.frame.addConstant($$.value)); self.emit(Ldr3, dst=[d], others=[ln]); return d .)
+reg: MEMI32(reg)      4 (. d = self.newTmp(); self.emit(Ldr2, dst=[d], src=[$1], others=[0]); return d .)
+reg: REGI32           1 (. return $$.value .)
+reg: CALL             1 (. return self.selector.munchCall($$.value) .)
 
 
+stmt: MOVI32(MEMI32(addr), reg) 3 (. self.emit(Str2, src=[$1, $2]) .)
+
+addr: reg 2 (. .)