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comparison python/target/arm.brg @ 323:e9fe6988497c

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Used burg for generating expressions
author Windel Bouwman
date Thu, 30 Jan 2014 19:03:24 +0100
parents 44f336460c2a
children d1ecc493384e
comparison
equal deleted inserted replaced
322:44f336460c2a 323:e9fe6988497c
1 1
2 from target.basetarget import Label, Comment, Alignment, LabelRef, DebugInfo, Nop
2 from target.arminstructions import Orr, Lsl, Str2, Ldr2, Ldr3 3 from target.arminstructions import Orr, Lsl, Str2, Ldr2, Ldr3
3 from target.arminstructions import B, Bl, Bgt, Blt, Beq, Bne 4 from target.arminstructions import B, Bl, Bgt, Blt, Beq, Bne
4 from target.arminstructions import Mov2, Mov3 5 from target.arminstructions import Mov2, Mov3
5 from target.arminstructions import Add, Sub, Cmp, Sub2, Add2, Mul 6 from target.arminstructions import Add, Sub, Cmp, Sub2, Add2, Mul
6 7
7 %% 8 %%
8 9
9 %terminal ADDI32 SUBI32 ORI32 SHLI32 10 %terminal ADDI32 SUBI32 MULI32
11 %terminal ORI32 SHLI32
10 %terminal CONSTI32 MEMI32 REGI32 CALL 12 %terminal CONSTI32 MEMI32 REGI32 CALL
13 %terminal MOVI32
11 14
12 %% 15 %%
13 16
17
14 reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add, dst=[d], src=[$1, $2]); return d .) 18 reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add, dst=[d], src=[$1, $2]); return d .)
15 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$1, $2]); return d .) 19 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$1, $2]); return d .)
16 reg: ORI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Orr, dst=[d], src=[$1, $2]); return d .) 20 reg: ORI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Orr, dst=[], src=[d, $2]); return d .)
17 reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Lsl, dst=[d], src=[$1, $2]); return d .) 21 reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Lsl, dst=[], src=[d, $2]); return d .)
18 reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Mul, dst=[d], src=[$1, $2]); return d .) 22 reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Mul, dst=[d], src=[$2, d]); return d .)
19 23
20 reg: CONSTI32 3 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$$.value]); return d .) 24 reg: CONSTI32 3 (. d = self.newTmp(); ln = LabelRef(self.selector.frame.addConstant($$.value)); self.emit(Ldr3, dst=[d], others=[ln]); return d .)
21 reg: MEMI32(reg) 4 (. d = self.newTmp(); self.emit(Ldr2, dst=[d], src=[$1]); return d .) 25 reg: MEMI32(reg) 4 (. d = self.newTmp(); self.emit(Ldr2, dst=[d], src=[$1], others=[0]); return d .)
22 reg: REGI32 1 (. pass .) 26 reg: REGI32 1 (. return $$.value .)
23 reg: CALL 1 (. pass .) 27 reg: CALL 1 (. return self.selector.munchCall($$.value) .)
24 28
25 29
30 stmt: MOVI32(MEMI32(addr), reg) 3 (. self.emit(Str2, src=[$1, $2]) .)
31
32 addr: reg 2 (. .)