--- a/python/ppci/target/x86/target_x86.py	Thu May 29 10:47:28 2014 +0200
+++ b/python/ppci/target/x86/target_x86.py	Thu May 29 12:13:37 2014 +0200
@@ -1,66 +1,59 @@
-from target import Register, Instruction, Target
-
-class x86Register(Register):
-   def __init__(self, name):
-      self.name = name
-
-class REG16(x86Register):
-   pass
-
-def addRegs(cls, names):
-   for name in names:
-      r = cls(name)
-      globals()[name] = r
-
-addRegs(REG16, ['ax', 'bx', 'cx'])
+from ..basetarget import Target
+from ...assembler import BaseAssembler
+from .registers import rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi
+from .registers import r8, r9, r10, r11, r12, r13, r14, r15, regs64
+from .instructions import Mov, Inc, Xor, Push, Pop
 
-regs = """
-ax; reg16
-"""
 
-class MO:
-   def __init__(self):
-      pass
-
-instrs = """
-add; 0x0; mem8/reg8; reg8
-"""
-
-# machine op table:
-mot = []
-
-for i in instrs.split('\n'):
-   i = i.strip()
-   if i:
-      print('INS:', i)
-      mnemonic, opcode, op1, op2 = [a.strip() for a in i.split(';')]
-      print(op1.split('/'), op2.split('/'))
+class X86Assembler(BaseAssembler):
+    def __init__(self, target):
+        super().__init__(target)
+        self.make_parser()
 
 
-print(mot)
+class X86Target(Target):
+    """ x86 target containing assembler, linker"""
+    def __init__(self):
+        super().__init__('x86')
 
-# Test first with these 3 instructions:
-"""
-mov reg64, reg64 : opcode=0x89
-xor reg64, reg64 : opcode=0x31
-inc reg64 : opcode=0xff
-"""
+        for reg in regs64:
+            self.add_keyword(reg.name)
 
-class x86Machine:
-   def __init__(self):
-      self.table = []
-      self.table.append((0x0, 'add', 'reg8/mem8, reg8'))
-      self.table.append((0x1, 'add', 'reg16/mem16/reg32/mem32, reg16/reg32'))
-      self.table.append((0x2, 'add', 'reg8, reg8/mem8'))
-   def forMnemonic(self, m):
-      return [i for i in self.table if i[1] == m]
-   def emit(self, m, ops):
-      print(m, ops)
-      ops = self.forMnemonic(m)
-      print(ops)
+        self.add_rule('reg', ['rax'], lambda rhs: rax)
+        self.add_rule('reg', ['rcx'], lambda rhs: rcx)
+        self.add_rule('reg', ['rdx'], lambda rhs: rdx)
+        self.add_rule('reg', ['rbx'], lambda rhs: rbx)
+        self.add_rule('reg', ['rsp'], lambda rhs: rsp)
+        self.add_rule('reg', ['rbp'], lambda rhs: rbp)
+        self.add_rule('reg', ['rsi'], lambda rhs: rsi)
+        self.add_rule('reg', ['rdi'], lambda rhs: rdi)
+        self.add_rule('reg', ['r8'], lambda rhs: r8)
+        self.add_rule('reg', ['r9'], lambda rhs: r9)
+        self.add_rule('reg', ['r10'], lambda rhs: r10)
+        self.add_rule('reg', ['r11'], lambda rhs: r11)
+        self.add_rule('reg', ['r12'], lambda rhs: r12)
+        self.add_rule('reg', ['r13'], lambda rhs: r13)
+        self.add_rule('reg', ['r14'], lambda rhs: r14)
+        self.add_rule('reg', ['r15'], lambda rhs: r15)
 
+        self.add_keyword('mov')
+        self.add_instruction(['mov', 'reg', ',', 'reg'],
+                             lambda rhs: Mov(rhs[1], rhs[3]))
 
-if __name__ == '__main__':
-   m = x86Machine()
-   m.emit('add', [ax, cx])
-   m.emit('mov', [bx, 1337])
+        self.add_keyword('xor')
+        self.add_instruction(['xor', 'reg', ',', 'reg'],
+                             lambda rhs: Xor(rhs[1], rhs[3]))
+
+        self.add_keyword('inc')
+        self.add_instruction(['inc', 'reg'],
+                             lambda rhs: Inc(rhs[1]))
+
+        self.add_keyword('push')
+        self.add_instruction(['push', 'reg'],
+                             lambda rhs: Push(rhs[1]))
+
+        self.add_keyword('pop')
+        self.add_instruction(['pop', 'reg'],
+                             lambda rhs: Pop(rhs[1]))
+
+        self.assembler = X86Assembler(self)