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comparison python/ppci/target/x86/target_x86.py @ 398:c0d9837acde8

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x86 target refactor
author Windel Bouwman
date Thu, 29 May 2014 12:13:37 +0200
parents 86b02c98a717
children
comparison
equal deleted inserted replaced
397:5d03c10fe19d 398:c0d9837acde8
1 from target import Register, Instruction, Target 1 from ..basetarget import Target
2 2 from ...assembler import BaseAssembler
3 class x86Register(Register): 3 from .registers import rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi
4 def __init__(self, name): 4 from .registers import r8, r9, r10, r11, r12, r13, r14, r15, regs64
5 self.name = name 5 from .instructions import Mov, Inc, Xor, Push, Pop
6
7 class REG16(x86Register):
8 pass
9
10 def addRegs(cls, names):
11 for name in names:
12 r = cls(name)
13 globals()[name] = r
14
15 addRegs(REG16, ['ax', 'bx', 'cx'])
16
17 regs = """
18 ax; reg16
19 """
20
21 class MO:
22 def __init__(self):
23 pass
24
25 instrs = """
26 add; 0x0; mem8/reg8; reg8
27 """
28
29 # machine op table:
30 mot = []
31
32 for i in instrs.split('\n'):
33 i = i.strip()
34 if i:
35 print('INS:', i)
36 mnemonic, opcode, op1, op2 = [a.strip() for a in i.split(';')]
37 print(op1.split('/'), op2.split('/'))
38 6
39 7
40 print(mot) 8 class X86Assembler(BaseAssembler):
41 9 def __init__(self, target):
42 # Test first with these 3 instructions: 10 super().__init__(target)
43 """ 11 self.make_parser()
44 mov reg64, reg64 : opcode=0x89
45 xor reg64, reg64 : opcode=0x31
46 inc reg64 : opcode=0xff
47 """
48
49 class x86Machine:
50 def __init__(self):
51 self.table = []
52 self.table.append((0x0, 'add', 'reg8/mem8, reg8'))
53 self.table.append((0x1, 'add', 'reg16/mem16/reg32/mem32, reg16/reg32'))
54 self.table.append((0x2, 'add', 'reg8, reg8/mem8'))
55 def forMnemonic(self, m):
56 return [i for i in self.table if i[1] == m]
57 def emit(self, m, ops):
58 print(m, ops)
59 ops = self.forMnemonic(m)
60 print(ops)
61 12
62 13
63 if __name__ == '__main__': 14 class X86Target(Target):
64 m = x86Machine() 15 """ x86 target containing assembler, linker"""
65 m.emit('add', [ax, cx]) 16 def __init__(self):
66 m.emit('mov', [bx, 1337]) 17 super().__init__('x86')
18
19 for reg in regs64:
20 self.add_keyword(reg.name)
21
22 self.add_rule('reg', ['rax'], lambda rhs: rax)
23 self.add_rule('reg', ['rcx'], lambda rhs: rcx)
24 self.add_rule('reg', ['rdx'], lambda rhs: rdx)
25 self.add_rule('reg', ['rbx'], lambda rhs: rbx)
26 self.add_rule('reg', ['rsp'], lambda rhs: rsp)
27 self.add_rule('reg', ['rbp'], lambda rhs: rbp)
28 self.add_rule('reg', ['rsi'], lambda rhs: rsi)
29 self.add_rule('reg', ['rdi'], lambda rhs: rdi)
30 self.add_rule('reg', ['r8'], lambda rhs: r8)
31 self.add_rule('reg', ['r9'], lambda rhs: r9)
32 self.add_rule('reg', ['r10'], lambda rhs: r10)
33 self.add_rule('reg', ['r11'], lambda rhs: r11)
34 self.add_rule('reg', ['r12'], lambda rhs: r12)
35 self.add_rule('reg', ['r13'], lambda rhs: r13)
36 self.add_rule('reg', ['r14'], lambda rhs: r14)
37 self.add_rule('reg', ['r15'], lambda rhs: r15)
38
39 self.add_keyword('mov')
40 self.add_instruction(['mov', 'reg', ',', 'reg'],
41 lambda rhs: Mov(rhs[1], rhs[3]))
42
43 self.add_keyword('xor')
44 self.add_instruction(['xor', 'reg', ',', 'reg'],
45 lambda rhs: Xor(rhs[1], rhs[3]))
46
47 self.add_keyword('inc')
48 self.add_instruction(['inc', 'reg'],
49 lambda rhs: Inc(rhs[1]))
50
51 self.add_keyword('push')
52 self.add_instruction(['push', 'reg'],
53 lambda rhs: Push(rhs[1]))
54
55 self.add_keyword('pop')
56 self.add_instruction(['pop', 'reg'],
57 lambda rhs: Pop(rhs[1]))
58
59 self.assembler = X86Assembler(self)