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comparison python/codegenarm.py @ 225:1c7364bd74c7

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Fixed pointer deref
author Windel Bouwman
date Thu, 11 Jul 2013 07:42:30 +0200
parents c3f1ce8b638f
children e621e3ba78d2
comparison
equal deleted inserted replaced
224:5af52987f5bd 225:1c7364bd74c7
1 import ir 1 import ir
2 from asmnodes import ALabel 2 from asmnodes import ALabel, AComment
3 import cortexm3 as arm 3 import cortexm3 as arm
4 from ppci import CompilerError 4 from ppci import CompilerError
5 5
6 class ArmCodeGenerator: 6 class ArmCodeGenerator:
7 """ 7 """
45 l, v = self.imms.pop() 45 l, v = self.imms.pop()
46 self.emit(ALabel(l)) 46 self.emit(ALabel(l))
47 self.emit(arm.dcd_ins(v)) 47 self.emit(arm.dcd_ins(v))
48 self.outs.align(4) 48 self.outs.align(4)
49 49
50 # Helper functions:
50 def getStack(self, v): 51 def getStack(self, v):
51 off = self.stack_frame.index(v) 52 off = self.stack_frame.index(v)
52 return off * 4 53 return off * 4
53 def addStack(self, v): 54 def addStack(self, v):
54 self.stack_frame.append(v) 55 self.stack_frame.append(v)
55 return self.getStack(v) 56 return self.getStack(v)
56 def getGlobal(self, r, g): 57 def getGlobal(self, r, g):
57 _global_address = g.name + '__global' 58 _global_address = g.name + '__global'
58 self.emit(arm.ldr_pcrel(r, ALabel(_global_address))) 59 self.emit(arm.ldr_pcrel(r, ALabel(_global_address)))
60 def loadStack(self, reg, val):
61 self.emit(arm.ldr_sprel(reg, arm.MemSpRel(self.getStack(val))))
62 def comment(self, txt):
63 self.emit(AComment(txt))
59 64
60 def generateInstruction(self, ins): 65 def generateInstruction(self, ins):
61 if type(ins) is ir.Branch: 66 if type(ins) is ir.Branch:
62 tgt = ALabel(ins.target.name) 67 tgt = ALabel(ins.target.name)
63 self.emit(arm.jmp_ins(tgt)) 68 self.emit(arm.jmp_ins(tgt))
64 elif type(ins) is ir.ImmLoad: 69 elif type(ins) is ir.ImmLoad:
70 self.comment(str(ins))
65 lname = ins.target.name + '_ivalue' 71 lname = ins.target.name + '_ivalue'
66 self.emit(arm.ldr_pcrel(arm.r0, ALabel(lname))) 72 self.emit(arm.ldr_pcrel(arm.r0, ALabel(lname)))
67 self.imms.append((lname, ins.value)) 73 self.imms.append((lname, ins.value))
68 self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.target)))) 74 self.emit(arm.str_sprel(arm.r0, arm.MemSpRel(self.addStack(ins.target))))
69 elif type(ins) is ir.Store: 75 elif type(ins) is ir.Store:
76 self.comment(str(ins))
70 # Load value in r0: 77 # Load value in r0:
71 self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.value)))) 78 self.loadStack(arm.r0, ins.value)
72 # store in memory: 79 # store in memory:
73 self.getGlobal(arm.r1, ins.location) 80 self.getGlobal(arm.r1, ins.location)
74 self.emit(arm.storeimm5_ins(arm.r0, arm.MemoryOp(arm.r1, 0))) 81 self.emit(arm.storeimm5_ins(arm.r0, arm.MemR8Rel(arm.r1, 0)))
75 elif type(ins) is ir.Load: 82 elif type(ins) is ir.Load:
83 self.comment(str(ins))
76 self.getGlobal(arm.r0, ins.location) 84 self.getGlobal(arm.r0, ins.location)
77 self.emit(arm.loadimm5_ins(arm.r0, arm.MemoryOp(arm.r0, 0))) 85 self.emit(arm.loadimm5_ins(arm.r0, arm.MemR8Rel(arm.r0, 0)))
78 # Store value on stack: 86 # Store value on stack:
79 self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.value)))) 87 self.emit(arm.str_sprel(arm.r0, arm.MemSpRel(self.addStack(ins.value))))
80 elif type(ins) is ir.BinaryOperator: 88 elif type(ins) is ir.BinaryOperator:
89 self.comment(str(ins))
81 # Load operands: 90 # Load operands:
82 self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.value1)))) 91 self.loadStack(arm.r0, ins.value1)
83 self.emit(arm.ldr_sprel(arm.r1, arm.MemoryOp(arm.sp, self.getStack(ins.value2)))) 92 self.loadStack(arm.r1, ins.value2)
84 # do operation: 93 # do operation:
85 if ins.operation == '+': 94 if ins.operation == '+':
86 self.emit(arm.addregs_ins(arm.r0, arm.r0, arm.r1)) 95 self.emit(arm.addregs_ins(arm.r0, arm.r0, arm.r1))
87 else: 96 else:
88 print('operation not implemented', ins.operation) 97 print('operation not implemented', ins.operation)
89 # Store value back: 98 # Store value back:
90 self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.result)))) 99 self.emit(arm.str_sprel(arm.r0, arm.MemSpRel(self.addStack(ins.result))))
91 elif type(ins) is ir.Return: 100 elif type(ins) is ir.Return:
101 self.comment(str(ins))
92 self.emit(arm.pop_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6, arm.r7, arm.pc}))) 102 self.emit(arm.pop_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
93 elif type(ins) is ir.ConditionalBranch: 103 elif type(ins) is ir.ConditionalBranch:
94 self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.a)))) 104 self.comment(str(ins))
95 self.emit(arm.ldr_sprel(arm.r1, arm.MemoryOp(arm.sp, self.getStack(ins.b)))) 105 self.loadStack(arm.r0, ins.a)
106 self.loadStack(arm.r1, ins.b)
96 self.emit(arm.cmp_ins(arm.r1, arm.r0)) 107 self.emit(arm.cmp_ins(arm.r1, arm.r0))
97 tgt_yes = ALabel(ins.lab1.name) 108 tgt_yes = ALabel(ins.lab1.name)
98 if ins.cond == '==': 109 if ins.cond == '==':
99 self.emit(arm.beq_ins(tgt_yes)) 110 self.emit(arm.beq_ins(tgt_yes))
100 else: 111 else: