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comparison python/target/armregisters.py @ 340:c7cc54c0dfdf devel

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author Windel Bouwman
date Sun, 23 Feb 2014 16:24:01 +0100
parents
children 4d204f6f7d4e
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339:6ee17c4dd6b8 340:c7cc54c0dfdf
1
2 from .basetarget import Register
3
4 class ArmRegister(Register):
5 def __init__(self, num, name):
6 super().__init__(name)
7 self.num = num
8
9 def __repr__(self):
10 return self.name
11
12
13 class Reg8Op(ArmRegister):
14 pass
15
16
17 class Reg16Op(ArmRegister):
18 pass
19
20
21 R0 = Reg8Op(0, 'r0')
22 R1 = Reg8Op(1, 'r1')
23 R2 = Reg8Op(2, 'r2')
24 R3 = Reg8Op(3, 'r3')
25 R4 = Reg8Op(4, 'r4')
26 R5 = Reg8Op(5, 'r5')
27 R6 = Reg8Op(6, 'r6')
28 R7 = Reg8Op(7, 'r7')
29 R7 = Reg8Op(8, 'r8')
30 R7 = Reg8Op(9, 'r9')
31 R7 = Reg8Op(10, 'r10')
32 R7 = Reg8Op(11, 'r11')
33 R7 = Reg8Op(12, 'r12')
34
35 # Other registers:
36 # TODO
37 SP = ArmRegister(13, 'sp')
38 LR = ArmRegister(14, 'lr')
39 PC = ArmRegister(15, 'pc')
40
41 registers = [R0, R1, R2, R3, R4, R5, R6, R7, SP, LR, PC]