--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/python/target/armregisters.py	Sun Feb 23 16:24:01 2014 +0100
@@ -0,0 +1,41 @@
+
+from .basetarget import Register
+
+class ArmRegister(Register):
+    def __init__(self, num, name):
+        super().__init__(name)
+        self.num = num
+
+    def __repr__(self):
+        return self.name
+
+
+class Reg8Op(ArmRegister):
+    pass
+
+
+class Reg16Op(ArmRegister):
+    pass
+
+
+R0 = Reg8Op(0, 'r0')
+R1 = Reg8Op(1, 'r1')
+R2 = Reg8Op(2, 'r2')
+R3 = Reg8Op(3, 'r3')
+R4 = Reg8Op(4, 'r4')
+R5 = Reg8Op(5, 'r5')
+R6 = Reg8Op(6, 'r6')
+R7 = Reg8Op(7, 'r7')
+R7 = Reg8Op(8, 'r8')
+R7 = Reg8Op(9, 'r9')
+R7 = Reg8Op(10, 'r10')
+R7 = Reg8Op(11, 'r11')
+R7 = Reg8Op(12, 'r12')
+
+# Other registers:
+# TODO
+SP = ArmRegister(13, 'sp')
+LR = ArmRegister(14, 'lr')
+PC = ArmRegister(15, 'pc')
+
+registers = [R0, R1, R2, R3, R4, R5, R6, R7, SP, LR, PC]