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comparison python/codegenarm.py @ 222:c3f1ce8b638f

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Fixup of parser
author Windel Bouwman
date Tue, 09 Jul 2013 17:36:31 +0200
parents 1fa3e0050b49
children 1c7364bd74c7
comparison
equal deleted inserted replaced
221:848c4b15fd0b 222:c3f1ce8b638f
63 self.emit(arm.jmp_ins(tgt)) 63 self.emit(arm.jmp_ins(tgt))
64 elif type(ins) is ir.ImmLoad: 64 elif type(ins) is ir.ImmLoad:
65 lname = ins.target.name + '_ivalue' 65 lname = ins.target.name + '_ivalue'
66 self.emit(arm.ldr_pcrel(arm.r0, ALabel(lname))) 66 self.emit(arm.ldr_pcrel(arm.r0, ALabel(lname)))
67 self.imms.append((lname, ins.value)) 67 self.imms.append((lname, ins.value))
68 self.emit(arm.str_sprel(arm.r0, self.addStack(ins.target))) 68 self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.target))))
69 elif type(ins) is ir.Store: 69 elif type(ins) is ir.Store:
70 # Load value in r0: 70 # Load value in r0:
71 self.emit(arm.ldr_sprel(arm.r0, self.getStack(ins.value))) 71 self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.value))))
72 # store in memory: 72 # store in memory:
73 self.getGlobal(arm.r1, ins.location) 73 self.getGlobal(arm.r1, ins.location)
74 self.emit(arm.storeimm5_ins(arm.r0, arm.MemoryOp(arm.r1, 0))) 74 self.emit(arm.storeimm5_ins(arm.r0, arm.MemoryOp(arm.r1, 0)))
75 elif type(ins) is ir.Load: 75 elif type(ins) is ir.Load:
76 self.getGlobal(arm.r0, ins.location) 76 self.getGlobal(arm.r0, ins.location)
77 self.emit(arm.loadimm5_ins(arm.r0, arm.MemoryOp(arm.r0, 0))) 77 self.emit(arm.loadimm5_ins(arm.r0, arm.MemoryOp(arm.r0, 0)))
78 # Store value on stack: 78 # Store value on stack:
79 self.emit(arm.str_sprel(arm.r0, self.addStack(ins.value))) 79 self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.value))))
80 elif type(ins) is ir.BinaryOperator: 80 elif type(ins) is ir.BinaryOperator:
81 # Load operands: 81 # Load operands:
82 self.emit(arm.ldr_sprel(arm.r0, self.getStack(ins.value1))) 82 self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.value1))))
83 self.emit(arm.ldr_sprel(arm.r1, self.getStack(ins.value2))) 83 self.emit(arm.ldr_sprel(arm.r1, arm.MemoryOp(arm.sp, self.getStack(ins.value2))))
84 # do operation: 84 # do operation:
85 if ins.operation == '+': 85 if ins.operation == '+':
86 self.emit(arm.addregs_ins(arm.r0, arm.r0, arm.r1)) 86 self.emit(arm.addregs_ins(arm.r0, arm.r0, arm.r1))
87 else: 87 else:
88 print('operation not implemented', ins.operation) 88 print('operation not implemented', ins.operation)
89 # Store value back: 89 # Store value back:
90 self.emit(arm.str_sprel(arm.r0, self.addStack(ins.result))) 90 self.emit(arm.str_sprel(arm.r0, arm.MemoryOp(arm.sp, self.addStack(ins.result))))
91 elif type(ins) is ir.Return: 91 elif type(ins) is ir.Return:
92 self.emit(arm.pop_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6, arm.r7, arm.pc}))) 92 self.emit(arm.pop_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
93 elif type(ins) is ir.ConditionalBranch: 93 elif type(ins) is ir.ConditionalBranch:
94 self.emit(arm.ldr_sprel(arm.r0, self.getStack(ins.a))) 94 self.emit(arm.ldr_sprel(arm.r0, arm.MemoryOp(arm.sp, self.getStack(ins.a))))
95 self.emit(arm.ldr_sprel(arm.r1, self.getStack(ins.b))) 95 self.emit(arm.ldr_sprel(arm.r1, arm.MemoryOp(arm.sp, self.getStack(ins.b))))
96 self.emit(arm.cmp_ins(arm.r1, arm.r0)) 96 self.emit(arm.cmp_ins(arm.r1, arm.r0))
97 tgt_yes = ALabel(ins.lab1.name) 97 tgt_yes = ALabel(ins.lab1.name)
98 if ins.cond == '==': 98 if ins.cond == '==':
99 self.emit(arm.beq_ins(tgt_yes)) 99 self.emit(arm.beq_ins(tgt_yes))
100 else: 100 else:
101 print('TODO', ins.cond) 101 print('TODO', ins.cond)
102 tgt_no = ALabel(ins.lab2.name) 102 tgt_no = ALabel(ins.lab2.name)
103 self.emit(arm.jmp_ins(tgt_no)) 103 self.emit(arm.jmp_ins(tgt_no))
104 elif type(ins) is ir.Alloc:
105 self.addStack(ins.value)
104 else: 106 else:
105 raise CompilerError('IR "{}" not covered'.format(ins)) 107 raise CompilerError('IR "{}" not covered'.format(ins))
106 108
107 109