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comparison test/testasm.py @ 381:6df89163e114

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Fix section and ldr pseudo instruction
author Windel Bouwman
date Sat, 26 Apr 2014 17:41:56 +0200
parents 442fb043d149
children 0c44e494ef58
comparison
equal deleted inserted replaced
380:67a584582aee 381:6df89163e114
1 #!/usr/bin/python 1 #!/usr/bin/python
2 2
3 import unittest 3 import unittest
4 from ppci import CompilerError 4 from ppci import CompilerError
5 from ppci.assembler import tokenize, Assembler, Lexer 5 from ppci.assembler import tokenize
6 from ppci.objectfile import ObjectFile 6 from ppci.objectfile import ObjectFile
7 from ppci.linker import Linker
8 from ppci.outstream import BinaryOutputStream 7 from ppci.outstream import BinaryOutputStream
9 from ppci.target.basetarget import Label 8 from ppci.target.basetarget import Label
9 from ppci.buildfunctions import link
10 10
11 11
12 class AssemblerLexingCase(unittest.TestCase): 12 class AssemblerLexingCase(unittest.TestCase):
13 """ Tests the assemblers lexer """ 13 """ Tests the assemblers lexer """
14 14
32 asmline = '0z4: mov rax, rbx $ ' 32 asmline = '0z4: mov rax, rbx $ '
33 with self.assertRaises(CompilerError): 33 with self.assertRaises(CompilerError):
34 list(tokenize(asmline, [])) 34 list(tokenize(asmline, []))
35 35
36 36
37 class AssemblerParsingTestCase(unittest.TestCase):
38 """
39 Tests the assembler parts
40 """
41 def setUp(self):
42 self.skipTest('refactoring asm parser')
43 self.parser = asmParser
44 self.stack = []
45
46 def emit(self, x):
47 self.stack.append(x)
48
49 def parse_line(self, line):
50 self.parser.parse(Lexer(line), self.emit)
51
52 def testParse(self):
53 asmline = 'lab1: mov rax, rbx'
54 self.parse_line(asmline)
55
56 def expectTree(self, asmline, stack):
57 self.parse_line(asmline)
58 self.assertSequenceEqual(stack, self.stack)
59
60 def testParse2(self):
61 asmline = 'a: mov rax, [rbx + 2]'
62 output = []
63 output.append(ALabel('a'))
64 output.append(AInstruction('mov', [ASymbol('rax'), AUnop('[]', ASymbol('rbx') + ANumber(2))]))
65 self.expectTree(asmline, output)
66
67 def testParse3(self):
68 # A label must be optional:
69 asmline = 'mov rax, 1'
70 output = [AInstruction('mov', [ASymbol('rax'), ANumber(1)])]
71 self.expectTree(asmline, output)
72
73 def testParse4(self):
74 # Test 3 operands:
75 asmline = 'add rax, [4*rbx + 22], rcx'
76 ops = []
77 ops.append(ASymbol('rax'))
78 ops.append(AUnop('[]', ANumber(4) * ASymbol('rbx') + ANumber(22)))
79 ops.append(ASymbol('rcx'))
80 output = [AInstruction('add', ops)]
81 self.expectTree(asmline, output)
82
83 def testParse5(self):
84 # An instruction must be optional:
85 asmline = 'lab1:'
86 output = []
87 output.append(ALabel('lab1'))
88 self.expectTree(asmline, output)
89
90 def testParse6(self):
91 # A line can be empty
92 self.parse_line('')
93
94
95 class OustreamTestCase(unittest.TestCase): 37 class OustreamTestCase(unittest.TestCase):
96 def test1(self): 38 def test1(self):
97 obj = ObjectFile() 39 obj = ObjectFile()
98 o = BinaryOutputStream(obj) 40 o = BinaryOutputStream(obj)
99 o.select_section('.text') 41 o.select_section('.text')
102 44
103 45
104 class AsmTestCaseBase(unittest.TestCase): 46 class AsmTestCaseBase(unittest.TestCase):
105 """ Base testcase for assembly """ 47 """ Base testcase for assembly """
106 def feed(self, line): 48 def feed(self, line):
107 self.a.assemble(line, self.ostream) 49 self.assembler.assemble(line, self.ostream)
108 50
109 def check(self, hexstr): 51 def check(self, hexstr, layout={}):
110 l = Linker() 52 self.assembler.flush()
111 self.obj = l.link([self.obj]) 53 self.obj = link([self.obj], layout)
112 data = bytes(self.obj.get_section('.text').data) 54 data = bytes(self.obj.get_section('.text').data)
113 self.assertSequenceEqual(bytes.fromhex(hexstr), data) 55 self.assertSequenceEqual(bytes.fromhex(hexstr), data)
114 56
115 57
116 if __name__ == '__main__': 58 if __name__ == '__main__':