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comparison python/adi.py @ 144:59a9a499e518

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Added adi class
author Windel Bouwman
date Sat, 09 Feb 2013 16:05:36 +0100
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143:1cc59ac80950 144:59a9a499e518
1
2 # Implementation of the ADI (ARM Debug Interface) v5 interface.
3
4 COMPONENT_CLASSES = {0x1: 'ROM table'}
5
6 class Adi:
7 def __init__(self, iface):
8 self.iface = iface
9 def r32(self, address):
10 return self.iface.read_debug32(address)
11 def w32(self, address, value):
12 self.iface.write_debug32(address, value)
13 def getId(self, offset):
14 print('reading id from {0:X}'.format(offset))
15 pid4 = self.r32(offset + 0xFD0)
16 #print('pid4', pid4)
17 pid5 = self.r32(offset + 0xFD4)
18 pid6 = self.r32(offset + 0xFD8)
19 pid7 = self.r32(offset + 0xFDC)
20 pid0 = self.r32(offset + 0xFE0)
21 pid1 = self.r32(offset + 0xFE4)
22 pid2 = self.r32(offset + 0xFE8)
23 pid3 = self.r32(offset + 0xFEC)
24 cid0 = self.r32(offset + 0xFF0)
25 cid1 = self.r32(offset + 0xFF4)
26 cid2 = self.r32(offset + 0xFF8)
27 cid3 = self.r32(offset + 0xFFC)
28 pids = [pid0, pid1, pid2, pid3, pid4, pid5, pid6, pid7]
29 cids = [cid0, cid1, cid2, cid3]
30 print('cids:', [hex(x) for x in cids], 'pids', [hex(x) for x in pids])
31 valid = cid0 == 0xD and (cid1 & 0xF) == 0x0 and cid2 == 0x5 and cid3 == 0xB1
32 if valid:
33 component_class = cid1 >> 4
34 else:
35 print('invalid class')
36 component_class = 0
37 # TODO: use pids
38 return component_class, pids
39
40 def parseRomTable(self, offset):
41 assert (offset & 0xFFF) == 0
42 component_class, pid = self.getId(offset)
43 assert component_class == 1
44 print('Component class:', COMPONENT_CLASSES[component_class])
45 print('memory also on this bus:', self.r32(offset + 0xFCC))
46 idx = 0
47 entry = self.r32(offset + idx * 4)
48 while entry != 0:
49 #print('Entry: {0:X}'.format(entry))
50 entryOffset = entry & 0xFFFFF000
51 cls, pids = self.getId((offset + entryOffset) & 0xFFFFFFFF)
52 print('class:', cls)
53 if cls == 9:
54 print('Debug block found!')
55
56 idx += 1
57 entry = self.r32(offset + idx * 4)
58
59