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comparison python/x86.py @ 174:3eb06f5fb987

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Added memory alloc for locals
author Windel Bouwman
date Fri, 19 Apr 2013 19:22:52 +0200
parents c1d2b6b9f9a7
children 460db5669efa
comparison
equal deleted inserted replaced
173:c1d2b6b9f9a7 174:3eb06f5fb987
33 33
34 def genBin(self, ir): 34 def genBin(self, ir):
35 self.asm = [] 35 self.asm = []
36 # Allocate registers: 36 # Allocate registers:
37 ra = registerallocator.RegisterAllocator() 37 ra = registerallocator.RegisterAllocator()
38 # TODO: do not register allocate on intermediate code:
38 ra.registerAllocate(ir, self.regs) 39 ra.registerAllocate(ir, self.regs)
39 self.genModule(ir) 40 self.genModule(ir)
40 return self.asm 41 return self.asm
41 42
42 def genModule(self, ir): 43 def genModule(self, ir):
43 #for f in ir.Functions: 44 for f in ir.Functions:
44 # self.genFunction(f) 45 self.genFunction(f)
45 for bb in ir.BasicBlocks:
46 self.genBB(bb)
47 def genFunction(self, f): 46 def genFunction(self, f):
48 self.emit('global {0}'.format(f.name)) 47 self.emit('global {0}'.format(f.name))
49 self.emit(AsmLabel(f.name)) 48 self.emit(AsmLabel(f.name))
49 self.emit(Jmp('jmp', f.entry.name))
50 for bb in f.BasicBlocks: 50 for bb in f.BasicBlocks:
51 self.genBB(bb) 51 self.genBB(bb)
52 def genBB(self, bb): 52 def genBB(self, bb):
53 self.emit(AsmLabel(bb.name)) 53 self.emit(AsmLabel(bb.name))
54 for i in bb.Instructions: 54 for i in bb.Instructions:
60 self.emit(Op('mov', i.result.reg, i.value1.reg)) 60 self.emit(Op('mov', i.result.reg, i.value1.reg))
61 self.emit(Op(ops[i.operation], i.result.reg, i.value2.reg)) 61 self.emit(Op(ops[i.operation], i.result.reg, i.value2.reg))
62 else: 62 else:
63 raise NotImplementedError('op {0}'.format(i.operation)) 63 raise NotImplementedError('op {0}'.format(i.operation))
64 elif type(i) is ir.Load: 64 elif type(i) is ir.Load:
65 self.emit(Op('mov', i.value, '[{0}]'.format(i.name))) 65 self.emit(Op('mov', i.value, '[{0}]'.format(i.location)))
66 elif type(i) is ir.Return: 66 elif type(i) is ir.Return:
67 self.emit('ret') 67 self.emit('ret')
68 elif type(i) is ir.Call: 68 elif type(i) is ir.Call:
69 self.emit('call') 69 self.emit('call')
70 elif type(i) is ir.ImmLoad: 70 elif type(i) is ir.ImmLoad:
71 self.emit(Op('mov', i.target, i.value)) 71 self.emit(Op('mov', i.target, i.value))
72 elif type(i) is ir.Store: 72 elif type(i) is ir.Store:
73 self.emit(Op('mov', '[{0}]'.format(i.name), i.value)) 73 self.emit(Op('mov', '[{0}]'.format(i.location), i.value))
74 elif type(i) is ir.ConditionalBranch: 74 elif type(i) is ir.ConditionalBranch:
75 self.emit(Op('cmp', i.a, i.b)) 75 self.emit(Op('cmp', i.a, i.b))
76 jmps = {'>':'jg', '<':'jl', '==':'je'} 76 jmps = {'>':'jg', '<':'jl', '==':'je'}
77 if i.cond in jmps: 77 if i.cond in jmps:
78 j = jmps[i.cond] 78 j = jmps[i.cond]
80 else: 80 else:
81 raise NotImplementedError('condition {0}'.format(i.cond)) 81 raise NotImplementedError('condition {0}'.format(i.cond))
82 self.emit(Jmp('jmp', i.lab2.name)) 82 self.emit(Jmp('jmp', i.lab2.name))
83 elif type(i) is ir.Branch: 83 elif type(i) is ir.Branch:
84 self.emit(Jmp('jmp', i.target.name)) 84 self.emit(Jmp('jmp', i.target.name))
85 elif type(i) is ir.Alloc:
86 pass
85 else: 87 else:
86 raise NotImplementedError('{0}'.format(i)) 88 raise NotImplementedError('{0}'.format(i))
87 89