annotate python/target/arminstructions.py @ 336:d1ecc493384e

Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
author Windel Bouwman
date Wed, 19 Feb 2014 22:32:15 +0100
parents 582a1aaa3983
children c7cc54c0dfdf
rev   line source
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1 import struct
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2 from ppci.asmnodes import ASymbol, AInstruction, ANumber, AUnop, ABinop
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3 from .basetarget import Register, Instruction, Target, Label, LabelRef
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4 from .basetarget import Imm32, Imm8, Imm7, Imm3
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5
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6
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7 def u16(h):
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8 return struct.pack('<H', h)
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9
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10 def u32(x):
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11 return struct.pack('<I', x)
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12
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13
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14 def val2bit(v, bits):
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15 b = []
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16 for i in range(bits):
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17 b.append(bool((1<<i) & v))
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18 #b.reverse()
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19 return b
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20
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21
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22 def bit_range(b, e):
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23 getter = lambda s: s[b:e]
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24 def setter(s, v):
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25 s[b:e] = v
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26 return property(getter, setter)
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27
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28 class ArmToken:
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29 def __init__(self):
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30 self.bit_value = 0
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31
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32 def set_bit(self, i, value):
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33 value = bool(value)
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34 assert i in range(0, 16)
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35 mask = 1 << i
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36 if value:
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37 self.bit_value |= mask
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38 else:
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39 self.bit_value &= (~mask)
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40
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41 def __getitem__(self, key):
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42 return False
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43
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44 def __setitem__(self, key, value):
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45 if type(key) is int:
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46 self.set_bit(key, value)
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47 elif type(key) is slice:
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48 assert key.step is None
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49 bits = key.stop - key.start
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50 value_bits = val2bit(value, bits)
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51 for i in range(key.start, key.stop):
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52 self.set_bit(i, value_bits[i - key.start])
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53 else:
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54 raise KeyError()
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55
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56 rd = bit_range(0, 3)
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57
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58 def encode(self):
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59 return u16(self.bit_value)
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60
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61
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62 # Operands:
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63
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64 class ArmRegister(Register):
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65 def __init__(self, num, name):
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66 super().__init__(name)
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67 self.num = num
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68
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69 def __repr__(self):
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70 return self.name
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71
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72 @classmethod
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73 def Create(cls, vop):
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74 if type(vop) is ASymbol:
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75 name = vop.name
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76 regs = {}
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77 for r in registers:
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78 regs[r.name] = r
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79 if name in regs:
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80 r = regs[name]
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81 if isinstance(r, cls):
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82 return r
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83
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84
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85 class Reg8Op(ArmRegister):
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86 pass
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87
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88
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89 class Reg16Op(ArmRegister):
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90 pass
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91
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92
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93 R0 = Reg8Op(0, 'r0')
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94 R1 = Reg8Op(1, 'r1')
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95 R2 = Reg8Op(2, 'r2')
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96 R3 = Reg8Op(3, 'r3')
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97 R4 = Reg8Op(4, 'r4')
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98 R5 = Reg8Op(5, 'r5')
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99 R6 = Reg8Op(6, 'r6')
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100 R7 = Reg8Op(7, 'r7')
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101 # Other registers:
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102 # TODO
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103 SP = ArmRegister(13, 'sp')
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104 LR = ArmRegister(14, 'lr')
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105 PC = ArmRegister(15, 'pc')
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106
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107 registers = [R0, R1, R2, R3, R4, R5, R6, R7, SP, LR, PC]
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108
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109
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110 class RegSpOp:
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111 @classmethod
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112 def Create(cls, vop):
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113 if type(vop) is ASymbol:
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114 if vop.name.lower() == 'sp':
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115 return cls()
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116
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117
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118 def getRegNum(n):
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119 for r in registers:
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120 if r.num == n:
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121 return r
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122
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123
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124 def getRegisterRange(n1, n2):
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125 regs = []
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126 if n1.num < n2.num:
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127 for n in range(n1.num, n2.num + 1):
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128 r = getRegNum(n)
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129 assert r
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130 regs.append(r)
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131 return regs
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132
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133
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134 def isRegOffset(regname, x, y):
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135 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname:
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136 return y.number
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137 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname:
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138 return x.number
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139
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140
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141 class MemRegXRel:
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142 def __init__(self, offset):
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143 assert offset % 4 == 0
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144 self.offset = offset
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145
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146 def __repr__(self):
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147 return '[{}, #{}]'.format(self.regname, self.offset)
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148
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149 @classmethod
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150 def Create(cls, vop):
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151 if type(vop) is AUnop and vop.operation == '[]' and type(vop.arg) is ABinop and vop.arg.op == '+':
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152 vop = vop.arg # descent
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153 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
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154 if type(offset) is int:
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155 if offset % 4 == 0:
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156 offset = vop.arg2.number
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157 return cls(offset)
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158 elif type(vop) is ASymbol and vop.name.upper() == self.regname:
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159 return cls(0)
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160
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161
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162 class MemSpRel(MemRegXRel):
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163 regname = 'SP'
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164
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165
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166 class MemR8Rel:
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167 def __init__(self, basereg, offset):
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168 assert type(basereg) is Reg8Op
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169 assert type(offset) is int
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170 self.basereg = basereg
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171 self.offset = offset
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172
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173 def __repr__(self):
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174 return '[{}, #{}]'.format(self.basereg, self.offset)
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175
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176 @classmethod
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177 def Create(cls, vop):
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178 if type(vop) is AUnop and vop.operation == '[]':
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179 vop = vop.arg # descent
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180 if type(vop) is ABinop:
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181 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
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182 offset = vop.arg2.number
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183 if offset > 120:
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184 return
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185 basereg = Reg8Op.Create(vop.arg1)
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186 if not basereg:
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187 return
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188 else:
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189 return
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190 elif type(vop) is ASymbol:
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191 offset = 0
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192 basereg = Reg8Op.Create(vop)
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193 if not basereg:
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194 return
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195 else:
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196 return
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197 return cls(getRegNum(basereg.num), offset)
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198
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199
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200 class RegisterSet:
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201 def __init__(self, regs):
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202 assert type(regs) is set
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203 self.regs = regs
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204
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205 def __repr__(self):
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206 return ','.join([str(r) for r in self.regs])
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207
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208 @classmethod
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209 def Create(cls, vop):
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210 assert type(vop) is AUnop and vop.operation == '{}'
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211 assert type(vop.arg) is list
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212 regs = set()
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213 for arg in vop.arg:
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214 if type(arg) is ASymbol:
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215 reg = ArmRegister.Create(arg)
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216 if not reg:
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217 return
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218 regs.add(reg)
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219 elif type(arg) is ABinop and arg.op == '-':
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220 reg1 = ArmRegister.Create(arg.arg1)
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221 reg2 = ArmRegister.Create(arg.arg2)
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222 if not reg1:
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223 return
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224 if not reg2:
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225 return
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226 for r in getRegisterRange(reg1, reg2):
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227 regs.add(r)
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228 else:
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229 raise Exception('Cannot be')
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230 return cls(regs)
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231
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232 def registerNumbers(self):
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233 return [r.num for r in self.regs]
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234
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235
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236
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237 # Instructions:
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238
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239 class ArmInstruction(Instruction):
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240 pass
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241
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242
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243 allins = []
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244
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245
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246 def instruction(i):
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247 allins.append(i)
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248 return i
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249
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250
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251 @instruction
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252 class Dcd(ArmInstruction):
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253 mnemonic = 'dcd'
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254 operands = (Imm32,)
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255 def __init__(self, expr):
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256 if isinstance(expr, Imm32):
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257 self.expr = expr.imm
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258 self.label = None
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259 elif isinstance(expr, LabelRef):
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260 self.expr = 0
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261 self.label = expr
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262 elif isinstance(expr, int):
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263 self.expr = expr
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264 self.label = None
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265 else:
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266 raise NotImplementedError()
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parents:
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267
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268 def encode(self):
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269 return u32(self.expr)
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270
335
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271 def relocations(self):
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diff changeset
272 assert not isinstance(self.expr, LabelRef)
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diff changeset
273 return []
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274
292
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275 def __repr__(self):
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276 return 'DCD 0x{0:X}'.format(self.expr)
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277
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278
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279 @instruction
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280 class nop_ins(ArmInstruction):
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281 mnemonic = 'nop'
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282 operands = tuple()
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283
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284 def encode(self):
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285 return bytes()
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286
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287 def __repr__(self):
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288 return 'NOP'
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289
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290
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291 # Memory related
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292
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293 class LS_imm5_base(ArmInstruction):
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parents:
diff changeset
294 """ ??? Rt, [Rn, imm5] """
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diff changeset
295 operands = (Reg8Op, MemR8Rel)
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parents:
diff changeset
296 def __init__(self, rt, memop):
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diff changeset
297 assert memop.offset % 4 == 0
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298 self.imm5 = memop.offset >> 2
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parents:
diff changeset
299 self.rn = memop.basereg.num
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diff changeset
300 self.rt = rt
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parents:
diff changeset
301 self.memloc = memop
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parents:
diff changeset
302 assert self.rn < 8
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parents:
diff changeset
303 assert self.rt.num < 8
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304
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305 def encode(self):
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parents:
diff changeset
306 Rn = self.rn
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parents:
diff changeset
307 Rt = self.rt.num
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parents:
diff changeset
308 imm5 = self.imm5
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parents:
diff changeset
309
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310 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
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311 return u16(h)
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312
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313
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314 def __repr__(self):
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315 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
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diff changeset
316
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diff changeset
317
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diff changeset
318 @instruction
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diff changeset
319 class Str2(LS_imm5_base):
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diff changeset
320 mnemonic = 'STR'
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321 opcode = 0xC
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322
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diff changeset
323 @classmethod
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diff changeset
324 def fromim(cls, im):
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diff changeset
325 mem = MemR8Rel(im.src[0], im.others[0])
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parents:
diff changeset
326 return cls(im.src[1], mem)
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diff changeset
327
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parents:
diff changeset
328
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parents:
diff changeset
329 @instruction
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diff changeset
330 class Ldr2(LS_imm5_base):
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parents:
diff changeset
331 mnemonic = 'LDR'
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diff changeset
332 opcode = 0xD
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diff changeset
333
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diff changeset
334 @classmethod
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parents:
diff changeset
335 def fromim(cls, im):
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diff changeset
336 mem = MemR8Rel(im.src[0], im.others[0])
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parents:
diff changeset
337 return cls(im.dst[0], mem)
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parents:
diff changeset
338
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diff changeset
339 class ls_sp_base_imm8(ArmInstruction):
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parents:
diff changeset
340 operands = (Reg8Op, MemSpRel)
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diff changeset
341 def __init__(self, rt, memop):
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342 self.rt = rt
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parents:
diff changeset
343 self.offset = memop.offset
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344
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345 def encode(self):
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parents:
diff changeset
346 rt = self.rt.num
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parents:
diff changeset
347 assert rt < 8
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parents:
diff changeset
348 imm8 = self.offset >> 2
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parents:
diff changeset
349 assert imm8 < 256
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parents:
diff changeset
350 h = (self.opcode << 8) | (rt << 8) | imm8
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parents:
diff changeset
351 return u16(h)
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parents:
diff changeset
352
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diff changeset
353 def __repr__(self):
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diff changeset
354 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset)
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parents:
diff changeset
355
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diff changeset
356 def align(x, m):
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parents:
diff changeset
357 while ((x % m) != 0):
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diff changeset
358 x = x + 1
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diff changeset
359 return x
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parents:
diff changeset
360
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parents:
diff changeset
361
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diff changeset
362 @instruction
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diff changeset
363 class Ldr3(ArmInstruction):
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parents:
diff changeset
364 """ ldr Rt, LABEL, load value from pc relative position """
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parents:
diff changeset
365 mnemonic = 'ldr'
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parents:
diff changeset
366 operands = (Reg8Op, LabelRef)
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parents:
diff changeset
367 def __init__(self, rt, label):
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parents:
diff changeset
368 assert isinstance(label, LabelRef)
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parents:
diff changeset
369 self.rt = rt
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parents:
diff changeset
370 self.label = label
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parents:
diff changeset
371 self.offset = 0
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parents:
diff changeset
372
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diff changeset
373 @classmethod
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parents:
diff changeset
374 def fromim(cls, im):
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parents:
diff changeset
375 return cls(im.dst[0], im.others[0])
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parents:
diff changeset
376
335
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
377 def relocations(self):
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
378 return [(self.label.name, 'lit_add_8')]
292
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
379
534b94b40aa8 Fixup reorganize
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diff changeset
380 def encode(self):
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
381 rt = self.rt.num
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parents:
diff changeset
382 assert rt < 8
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Windel Bouwman
parents:
diff changeset
383 assert self.offset % 4 == 0
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
384 imm8 = self.offset >> 2
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
385 assert imm8 < 256
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
386 assert imm8 >= 0
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
387 h = (0x9 << 11) | (rt << 8) | imm8
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
388 return u16(h)
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parents:
diff changeset
389
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parents:
diff changeset
390 def __repr__(self):
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parents:
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391 return 'LDR {}, {}'.format(self.rt, self.label.name)
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parents:
diff changeset
392
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parents:
diff changeset
393
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parents:
diff changeset
394 @instruction
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parents:
diff changeset
395 class Ldr1(ls_sp_base_imm8):
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parents:
diff changeset
396 """ ldr Rt, [SP, imm8] """
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parents:
diff changeset
397 mnemonic = 'LDR'
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parents:
diff changeset
398 opcode = 0x98
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parents:
diff changeset
399
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parents:
diff changeset
400
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parents:
diff changeset
401 @instruction
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parents:
diff changeset
402 class Str1(ls_sp_base_imm8):
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parents:
diff changeset
403 """ str Rt, [SP, imm8] """
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parents:
diff changeset
404 mnemonic = 'STR'
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parents:
diff changeset
405 opcode = 0x90
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parents:
diff changeset
406
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parents:
diff changeset
407
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Windel Bouwman
parents:
diff changeset
408 @instruction
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parents:
diff changeset
409 class Mov3(ArmInstruction):
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Windel Bouwman
parents:
diff changeset
410 """ mov Rd, imm8, move immediate value into register """
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parents:
diff changeset
411 mnemonic = 'mov'
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parents:
diff changeset
412 opcode = 4 # 00100 Rd(3) imm8
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
413 operands = (Reg8Op, Imm8)
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Windel Bouwman
parents:
diff changeset
414 def __init__(self, rd, imm):
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parents:
diff changeset
415 if type(imm) is int:
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parents:
diff changeset
416 imm = Imm8(imm)
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parents:
diff changeset
417 assert type(imm) is Imm8
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parents:
diff changeset
418 self.imm = imm.imm
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parents:
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419 assert type(rd) is Reg8Op, str(type(rd))
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parents:
diff changeset
420 self.rd = rd
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parents:
diff changeset
421
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diff changeset
422 @classmethod
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parents:
diff changeset
423 def fromim(cls, im):
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parents:
diff changeset
424 return cls(im.dst[0], im.others[0])
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parents:
diff changeset
425
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parents:
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426 def encode(self):
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parents:
diff changeset
427 rd = self.rd.num
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parents:
diff changeset
428 opcode = self.opcode
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parents:
diff changeset
429 imm8 = self.imm
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parents:
diff changeset
430 h = (opcode << 11) | (rd << 8) | imm8
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parents:
diff changeset
431 return u16(h)
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parents:
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432
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parents:
diff changeset
433 def __repr__(self):
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parents:
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434 return 'MOV {}, {}'.format(self.rd, self.imm)
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parents:
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435
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Windel Bouwman
parents:
diff changeset
436
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437
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parents:
diff changeset
438 # Arithmatics:
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parents:
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439
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parents:
diff changeset
440
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Windel Bouwman
parents:
diff changeset
441
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parents:
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442 class regregimm3_base(ArmInstruction):
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parents:
diff changeset
443 operands = (Reg8Op, Reg8Op, Imm3)
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Windel Bouwman
parents:
diff changeset
444 def __init__(self, rd, rn, imm3):
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parents:
diff changeset
445 self.rd = rd
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parents:
diff changeset
446 self.rn = rn
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Windel Bouwman
parents:
diff changeset
447 assert type(imm3) is Imm3
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parents:
diff changeset
448 self.imm3 = imm3
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parents:
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449
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Windel Bouwman
parents:
diff changeset
450 @classmethod
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parents:
diff changeset
451 def fromim(cls, im):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
452 return cls(im.dst[0], im.src[0], im.others[0])
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Windel Bouwman
parents:
diff changeset
453
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parents:
diff changeset
454 def encode(self):
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parents:
diff changeset
455 rd = self.rd.num
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Windel Bouwman
parents:
diff changeset
456 rn = self.rn.num
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parents:
diff changeset
457 imm3 = self.imm3.imm
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parents:
diff changeset
458 opcode = self.opcode
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parents:
diff changeset
459 h = (self.opcode << 9) | (imm3 << 6) | (rn << 3) | rd
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parents:
diff changeset
460 return u16(h)
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parents:
diff changeset
461
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parents:
diff changeset
462 def __repr__(self):
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parents:
diff changeset
463 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.imm3.imm)
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Windel Bouwman
parents:
diff changeset
464
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465 @instruction
300
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parents: 292
diff changeset
466 class Add2(regregimm3_base):
292
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parents:
diff changeset
467 """ add Rd, Rn, imm3 """
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parents:
diff changeset
468 mnemonic = 'add'
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
469 opcode = 0b0001110
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Windel Bouwman
parents:
diff changeset
470
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parents:
diff changeset
471
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parents:
diff changeset
472 @instruction
300
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parents: 292
diff changeset
473 class Sub2(regregimm3_base):
292
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parents:
diff changeset
474 """ sub Rd, Rn, imm3 """
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Windel Bouwman
parents:
diff changeset
475 mnemonic = 'sub'
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parents:
diff changeset
476 opcode = 0b0001111
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Windel Bouwman
parents:
diff changeset
477
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Windel Bouwman
parents:
diff changeset
478
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parents:
diff changeset
479 class regregreg_base(ArmInstruction):
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Windel Bouwman
parents:
diff changeset
480 """ ??? Rd, Rn, Rm """
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Windel Bouwman
parents:
diff changeset
481 operands = (Reg8Op, Reg8Op, Reg8Op)
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Windel Bouwman
parents:
diff changeset
482 def __init__(self, rd, rn, rm):
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parents:
diff changeset
483 self.rd = rd
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
484 self.rn = rn
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parents:
diff changeset
485 self.rm = rm
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parents:
diff changeset
486
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Windel Bouwman
parents:
diff changeset
487 @classmethod
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Windel Bouwman
parents:
diff changeset
488 def fromim(cls, im):
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Windel Bouwman
parents:
diff changeset
489 return cls(im.dst[0], im.src[0], im.src[1])
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
490
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parents:
diff changeset
491 def encode(self):
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
492 at = ArmToken()
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parents: 335
diff changeset
493 at.rd = self.rd.num
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
494 rn = self.rn.num
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Windel Bouwman
parents:
diff changeset
495 rm = self.rm.num
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
496 at[3:6] = rn
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
497 at[6:9] = rm
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
498 at[9:16] = self.opcode
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
499 #h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
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parents: 335
diff changeset
500 #return u16(h)
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
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parents: 335
diff changeset
501 return at.encode()
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
502
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Windel Bouwman
parents:
diff changeset
503 def __repr__(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
504 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
505
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
506
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
507 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
508 class Add(regregreg_base):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
509 mnemonic = 'ADD'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
510 opcode = 0b0001100
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
511
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
512
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
513 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
514 class Sub(regregreg_base):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
515 mnemonic = 'SUB'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
516 opcode = 0b0001101
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
517
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
518
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
519 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
520 class Mov2(ArmInstruction):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
521 """ mov rd, rm """
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
522 operands = (ArmRegister, ArmRegister)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
523 mnemonic = 'MOV'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
524 def __init__(self, rd, rm):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
525 self.rd = rd
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
526 self.rm = rm
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
527
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
528 @classmethod
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
529 def fromim(cls, im):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
530 return cls(im.dst[0], im.src[0])
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
531
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
532 def encode(self):
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
533 at = ArmToken()
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
534 at.rd = self.rd.num & 0x7
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
535 D = (self.rd.num >> 3) & 0x1
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
536 Rm = self.rm.num
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
537 opcode = 0b01000110
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
538 at[8:16] = opcode
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
539 at[3:7] = Rm
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
540 at[7] = D
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
541 return at.encode() # u16((opcode << 8) | (D << 7) |(Rm << 3) | Rd)
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
542
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
543 def __repr__(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
544 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm)
335
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
545
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
546
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
547 @instruction
300
Windel Bouwman
parents: 292
diff changeset
548 class Mul(ArmInstruction):
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
549 """ mul Rn, Rdm """
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
550 operands = (Reg8Op, Reg8Op)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
551 mnemonic = 'MUL'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
552 def __init__(self, rn, rdm):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
553 self.rn = rn
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
554 self.rdm = rdm
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
555
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
556 @classmethod
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
557 def fromim(cls, im):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
558 assert im.src[1] is im.dst[0]
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
559 return cls(im.src[0], im.dst[0])
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
560
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
561 def encode(self):
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
562 at = ArmToken()
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
563 rn = self.rn.num
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
564 at.rd = self.rdm.num
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
565 opcode = 0b0100001101
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
566 #h = (opcode << 6) | (rn << 3) | rdm
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
567 at[6:16] = opcode
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
568 at[3:6] = rn
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
569 return at.encode()
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
570
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
571 def __repr__(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
572 return '{} {}, {}'.format(self.mnemonic, self.rn, self.rdm)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
573
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
574
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
575 class regreg_base(ArmInstruction):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
576 """ ??? Rdn, Rm """
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
577 operands = (Reg8Op, Reg8Op)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
578 # TODO: integrate with the code gen interface:
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
579 src = (0, 1)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
580 dst = (0,)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
581 def __init__(self, rdn, rm):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
582 self.rdn = rdn
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
583 self.rm = rm
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
584
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
585 @classmethod
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
586 def fromim(cls, im):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
587 return cls(im.src[0], im.src[1])
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
588
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
589 def encode(self):
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
590 at = ArmToken()
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
591 at.rd = self.rdn.num
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
592 rm = self.rm.num
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
593 at[3:6] = rm
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
594 at[6:16] = self.opcode
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
595 return at.encode()
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
596
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
597 def __repr__(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
598 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
599
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
600
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
601 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
602 class movregreg_ins(regreg_base):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
603 """ mov Rd, Rm (reg8 operands) """
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
604 mnemonic = 'mov'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
605 opcode = 0
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
606
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
607
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
608 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
609 class And(regreg_base):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
610 mnemonic = 'AND'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
611 opcode = 0b0100000000
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
612
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
613
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
614 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
615 class Orr(regreg_base):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
616 mnemonic = 'ORR'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
617 opcode = 0b0100001100
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
618
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
619
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
620 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
621 class Cmp(regreg_base):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
622 mnemonic = 'CMP'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
623 opcode = 0b0100001010
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
624
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
625
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
626 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
627 class Lsl(regreg_base):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
628 mnemonic = 'LSL'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
629 opcode = 0b0100000010
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
630
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
631
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
632 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
633 class cmpregimm8_ins(ArmInstruction):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
634 """ cmp Rn, imm8 """
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
635 mnemonic = 'cmp'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
636 opcode = 5 # 00101
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
637 operands = (Reg8Op, Imm8)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
638 def __init__(self, rn, imm):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
639 self.rn = rn
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
640 self.imm = imm
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
641
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
642 def encode(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
643 rn = self.rn.num
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
644 imm = self.imm.imm
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
645 opcode = self.opcode
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
646 h = (opcode << 11) | (rn << 8) | imm
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
647 return u16(h)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
648
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
649
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
650 # Jumping:
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
651
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
652 def wrap_negative(x, bits):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
653 b = struct.unpack('<I', struct.pack('<i', x))[0]
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
654 mask = (1 << bits) - 1
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
655 return b & mask
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
656
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
657 class jumpBase_ins(ArmInstruction):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
658 operands = (LabelRef,)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
659 def __init__(self, target_label):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
660 assert type(target_label) is LabelRef
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
661 self.target = target_label
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
662 self.offset = 0
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
663
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
664 def __repr__(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
665 return '{} {}'.format(self.mnemonic, self.target.name)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
666
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
667
335
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
668 class Imm11Reloc:
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
669 def apply(self, P, S):
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
670 pass
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
671
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
672
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
673 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
674 class B(jumpBase_ins):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
675 mnemonic = 'B'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
676 def encode(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
677 imm11 = wrap_negative(self.offset >> 1, 11)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
678 h = (0b11100 << 11) | imm11 # | 1 # 1 to enable thumb mode
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
679 return u16(h)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
680
335
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
681 def relocations(self):
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
682 return [(self.target.name, 'wrap_new11')]
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
683
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
684 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
685 class Bl(jumpBase_ins):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
686 mnemonic = 'BL'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
687 def encode(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
688 imm32 = wrap_negative(self.offset >> 1, 32)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
689 imm11 = imm32 & 0x7FF
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
690 imm10 = (imm32 >> 11) & 0x3FF
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
691 j1 = 1 # TODO: what do these mean?
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
692 j2 = 1
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
693 s = (imm32 >> 24) & 0x1
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
694 h1 = (0b11110 << 11) | (s << 10) | imm10
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
695 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
696 return u16(h1) + u16(h2)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
697
335
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
698 def relocations(self):
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
699 return [(self.target.name, 'bl_imm11_imm10')]
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
700
335
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
701
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
702 class cond_base_ins(jumpBase_ins):
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
703 def encode(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
704 imm8 = wrap_negative(self.offset >> 1, 8)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
705 h = (0b1101 << 12) | (self.cond << 8) | imm8
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
706 return u16(h)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
707
335
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
708 def relocations(self):
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
709 return [(self.target.name, 'rel8')]
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
710
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
711
336
d1ecc493384e Added spiffy armtoken class for bit fiddeling. Added cool test that checks for build repeatability
Windel Bouwman
parents: 335
diff changeset
712 class cond_base_ins_long(jumpBase_ins):
335
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
713 """ Encoding T3 """
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
714 def encode(self):
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
715 j1 = 1 # TODO: what do these mean?
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
716 j2 = 1
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
717 h1 = (0b11110 << 11) | (self.cond << 6)
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
718 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11)
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
719 return u16(h1) + u16(h2)
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
720
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
721 def relocations(self):
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
722 return [(self.target.name, 'b_imm11_imm6')]
582a1aaa3983 Added long branch format
Windel Bouwman
parents: 334
diff changeset
723
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
724
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
725 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
726 class Beq(cond_base_ins):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
727 mnemonic = 'beq'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
728 cond = 0
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
729
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
730
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
731 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
732 class Bne(cond_base_ins):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
733 mnemonic = 'bne'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
734 cond = 1
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
735
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
736
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
737 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
738 class Blt(cond_base_ins):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
739 mnemonic = 'blt'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
740 cond = 0b1011
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
741
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
742
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
743 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
744 class Bgt(cond_base_ins):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
745 mnemonic = 'bgt'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
746 cond = 0b1100
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
747
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
748
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
749 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
750 class Push(ArmInstruction):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
751 operands = (RegisterSet,)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
752 mnemonic = 'push'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
753
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
754 def __init__(self, regs):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
755 if type(regs) is set:
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
756 regs = RegisterSet(regs)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
757 assert (type(regs),) == self.operands, (type(regs),)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
758 self.regs = regs
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
759
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
760 def __repr__(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
761 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
762
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
763 def encode(self):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
764 reg_list = 0
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
765 M = 0
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
766 for n in self.regs.registerNumbers():
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
767 if n < 8:
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
768 reg_list |= (1 << n)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
769 elif n == 14:
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
770 M = 1
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
771 else:
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
772 raise NotImplementedError('not implemented for this register')
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
773 h = (0x5a << 9) | (M << 8) | reg_list
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
774 return u16(h)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
775
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
776
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
777 @instruction
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
778 class Pop(ArmInstruction):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
779 operands = (RegisterSet,)
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
780 mnemonic = 'pop'
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
781
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
782 def __init__(self, regs):
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
783 if type(regs) is set:
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784 regs = RegisterSet(regs)
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785 assert (type(regs),) == self.operands, (type(regs),)
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786 self.regs = regs
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787
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788 def __repr__(self):
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789 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
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790
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791 def encode(self):
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792 reg_list = 0
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793 P = 0
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794 for n in self.regs.registerNumbers():
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795 if n < 8:
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796 reg_list |= (1 << n)
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797 elif n == 15:
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798 P = 1
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799 else:
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800 raise NotImplementedError('not implemented for this register')
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801 h = (0x5E << 9) | (P << 8) | reg_list
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802 return u16(h)
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parents:
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803
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804
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805 @instruction
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806 class Yield(ArmInstruction):
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807 operands = ()
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808 mnemonic = 'yield'
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809
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810 def encode(self):
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811 return u16(0xbf10)
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812
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813 # misc:
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814
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815 # add/sub SP:
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816 class addspsp_base(ArmInstruction):
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817 operands = (RegSpOp, RegSpOp, Imm7)
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818 def __init__(self, _sp, _sp2, imm7):
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819 self.imm7 = imm7.imm
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820 assert self.imm7 % 4 == 0
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821 self.imm7 >>= 2
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822
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823 def encode(self):
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parents:
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824 return u16((self.opcode << 7) |self.imm7)
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825
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826 def __repr__(self):
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parents:
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827 return '{} sp, sp, {}'.format(self.mnemonic, self.imm7 << 2)
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parents:
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828
305
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diff changeset
829
292
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parents:
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830 @instruction
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parents:
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831 class AddSp(addspsp_base):
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parents:
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832 mnemonic = 'add'
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parents:
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833 opcode = 0b101100000
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parents:
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834
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parents:
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835
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parents:
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836 @instruction
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parents:
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837 class SubSp(addspsp_base):
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parents:
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838 mnemonic = 'sub'
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parents:
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839 opcode = 0b101100001