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292
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1 import struct
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334
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2 from ppci.asmnodes import ASymbol, AInstruction, ANumber, AUnop, ABinop
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292
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3 from .basetarget import Register, Instruction, Target, Label, LabelRef
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4 from .basetarget import Imm32, Imm8, Imm7, Imm3
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5
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6
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7 def u16(h):
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8 return struct.pack('<H', h)
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9
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10 def u32(x):
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11 return struct.pack('<I', x)
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12
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13 # Operands:
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14
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15 class ArmRegister(Register):
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16 def __init__(self, num, name):
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17 super().__init__(name)
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18 self.num = num
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19
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20 def __repr__(self):
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21 return self.name
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22
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23 @classmethod
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24 def Create(cls, vop):
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25 if type(vop) is ASymbol:
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26 name = vop.name
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27 regs = {}
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28 for r in registers:
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29 regs[r.name] = r
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30 if name in regs:
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31 r = regs[name]
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32 if isinstance(r, cls):
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33 return r
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34
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35
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36 class Reg8Op(ArmRegister):
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37 pass
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38
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39
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40 class Reg16Op(ArmRegister):
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41 pass
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42
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43
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44 R0 = Reg8Op(0, 'r0')
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45 R1 = Reg8Op(1, 'r1')
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46 R2 = Reg8Op(2, 'r2')
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47 R3 = Reg8Op(3, 'r3')
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48 R4 = Reg8Op(4, 'r4')
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49 R5 = Reg8Op(5, 'r5')
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50 R6 = Reg8Op(6, 'r6')
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51 R7 = Reg8Op(7, 'r7')
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52 # Other registers:
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53 # TODO
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54 SP = ArmRegister(13, 'sp')
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55 LR = ArmRegister(14, 'lr')
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56 PC = ArmRegister(15, 'pc')
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57
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58 registers = [R0, R1, R2, R3, R4, R5, R6, R7, SP, LR, PC]
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59
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60
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61 class RegSpOp:
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62 @classmethod
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63 def Create(cls, vop):
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64 if type(vop) is ASymbol:
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65 if vop.name.lower() == 'sp':
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66 return cls()
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67
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68
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69 def getRegNum(n):
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70 for r in registers:
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71 if r.num == n:
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72 return r
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73
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74
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75 def getRegisterRange(n1, n2):
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76 regs = []
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77 if n1.num < n2.num:
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78 for n in range(n1.num, n2.num + 1):
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79 r = getRegNum(n)
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80 assert r
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81 regs.append(r)
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82 return regs
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83
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84
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85 def isRegOffset(regname, x, y):
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86 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname:
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87 return y.number
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88 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname:
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89 return x.number
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90
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91
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92 class MemRegXRel:
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93 def __init__(self, offset):
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94 assert offset % 4 == 0
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95 self.offset = offset
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96
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97 def __repr__(self):
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98 return '[{}, #{}]'.format(self.regname, self.offset)
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99
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100 @classmethod
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101 def Create(cls, vop):
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102 if type(vop) is AUnop and vop.operation == '[]' and type(vop.arg) is ABinop and vop.arg.op == '+':
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103 vop = vop.arg # descent
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104 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
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105 if type(offset) is int:
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106 if offset % 4 == 0:
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107 offset = vop.arg2.number
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108 return cls(offset)
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109 elif type(vop) is ASymbol and vop.name.upper() == self.regname:
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110 return cls(0)
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111
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112
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113 class MemSpRel(MemRegXRel):
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114 regname = 'SP'
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115
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116
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117 class MemR8Rel:
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118 def __init__(self, basereg, offset):
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119 assert type(basereg) is Reg8Op
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120 assert type(offset) is int
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121 self.basereg = basereg
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122 self.offset = offset
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123
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124 def __repr__(self):
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125 return '[{}, #{}]'.format(self.basereg, self.offset)
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126
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127 @classmethod
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128 def Create(cls, vop):
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129 if type(vop) is AUnop and vop.operation == '[]':
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130 vop = vop.arg # descent
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131 if type(vop) is ABinop:
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132 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
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133 offset = vop.arg2.number
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134 if offset > 120:
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135 return
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136 basereg = Reg8Op.Create(vop.arg1)
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137 if not basereg:
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138 return
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139 else:
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140 return
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141 elif type(vop) is ASymbol:
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142 offset = 0
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143 basereg = Reg8Op.Create(vop)
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144 if not basereg:
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145 return
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146 else:
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147 return
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148 return cls(getRegNum(basereg.num), offset)
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149
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150
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151 class RegisterSet:
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152 def __init__(self, regs):
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153 assert type(regs) is set
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154 self.regs = regs
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155
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156 def __repr__(self):
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157 return ','.join([str(r) for r in self.regs])
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158
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159 @classmethod
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160 def Create(cls, vop):
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161 assert type(vop) is AUnop and vop.operation == '{}'
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162 assert type(vop.arg) is list
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163 regs = set()
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164 for arg in vop.arg:
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165 if type(arg) is ASymbol:
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166 reg = ArmRegister.Create(arg)
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167 if not reg:
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168 return
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169 regs.add(reg)
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170 elif type(arg) is ABinop and arg.op == '-':
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171 reg1 = ArmRegister.Create(arg.arg1)
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172 reg2 = ArmRegister.Create(arg.arg2)
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173 if not reg1:
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174 return
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175 if not reg2:
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176 return
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177 for r in getRegisterRange(reg1, reg2):
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178 regs.add(r)
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179 else:
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180 raise Exception('Cannot be')
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181 return cls(regs)
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182
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183 def registerNumbers(self):
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184 return [r.num for r in self.regs]
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185
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186
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187
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188 # Instructions:
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189
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190 class ArmInstruction(Instruction):
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191 pass
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192
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193
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194 allins = []
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195
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196
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197 def instruction(i):
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198 allins.append(i)
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199 return i
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200
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201
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202 @instruction
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203 class Dcd(ArmInstruction):
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204 mnemonic = 'dcd'
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205 operands = (Imm32,)
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206 def __init__(self, expr):
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207 if isinstance(expr, Imm32):
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208 self.expr = expr.imm
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209 self.label = None
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210 elif isinstance(expr, LabelRef):
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211 self.expr = 0
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212 self.label = expr
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213 elif isinstance(expr, int):
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214 self.expr = expr
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215 self.label = None
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216 else:
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217 raise NotImplementedError()
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218
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219 def resolve(self, f):
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220 if self.label:
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221 self.expr = f(self.label.name)
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222
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223 def encode(self):
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224 return u32(self.expr)
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225
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226 def __repr__(self):
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227 return 'DCD 0x{0:X}'.format(self.expr)
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228
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229
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230 @instruction
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231 class nop_ins(ArmInstruction):
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232 mnemonic = 'nop'
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233 operands = tuple()
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234
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235 def encode(self):
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236 return bytes()
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237
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238 def __repr__(self):
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239 return 'NOP'
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240
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241
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242 # Memory related
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243
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244 class LS_imm5_base(ArmInstruction):
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245 """ ??? Rt, [Rn, imm5] """
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246 operands = (Reg8Op, MemR8Rel)
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247 def __init__(self, rt, memop):
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248 assert memop.offset % 4 == 0
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249 self.imm5 = memop.offset >> 2
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250 self.rn = memop.basereg.num
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251 self.rt = rt
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252 self.memloc = memop
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253 assert self.rn < 8
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254 assert self.rt.num < 8
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255
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256 def encode(self):
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257 Rn = self.rn
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258 Rt = self.rt.num
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259 imm5 = self.imm5
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260
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261 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
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262 return u16(h)
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263
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264
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265 def __repr__(self):
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266 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
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267
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268
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269 @instruction
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270 class Str2(LS_imm5_base):
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271 mnemonic = 'STR'
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272 opcode = 0xC
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273
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274 @classmethod
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275 def fromim(cls, im):
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276 mem = MemR8Rel(im.src[0], im.others[0])
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277 return cls(im.src[1], mem)
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278
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279
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280 @instruction
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281 class Ldr2(LS_imm5_base):
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282 mnemonic = 'LDR'
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283 opcode = 0xD
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284
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285 @classmethod
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286 def fromim(cls, im):
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287 mem = MemR8Rel(im.src[0], im.others[0])
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288 return cls(im.dst[0], mem)
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289
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290 class ls_sp_base_imm8(ArmInstruction):
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291 operands = (Reg8Op, MemSpRel)
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292 def __init__(self, rt, memop):
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293 self.rt = rt
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294 self.offset = memop.offset
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295
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296 def encode(self):
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297 rt = self.rt.num
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298 assert rt < 8
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299 imm8 = self.offset >> 2
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300 assert imm8 < 256
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301 h = (self.opcode << 8) | (rt << 8) | imm8
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302 return u16(h)
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303
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304 def __repr__(self):
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305 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset)
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306
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307 def align(x, m):
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308 while ((x % m) != 0):
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309 x = x + 1
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310 return x
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311
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312
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313 @instruction
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314 class Ldr3(ArmInstruction):
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315 """ ldr Rt, LABEL, load value from pc relative position """
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316 mnemonic = 'ldr'
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317 operands = (Reg8Op, LabelRef)
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318 def __init__(self, rt, label):
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319 assert isinstance(label, LabelRef)
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320 self.rt = rt
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321 self.label = label
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322 self.offset = 0
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323
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324 @classmethod
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325 def fromim(cls, im):
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326 return cls(im.dst[0], im.others[0])
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327
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328 def resolve(self, f):
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329 la = f(self.label.name)
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330 sa = align(self.address + 2, 4)
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331 self.offset = (la - sa)
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332 if self.offset < 0:
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333 self.offset = 0
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334
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335 def encode(self):
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336 rt = self.rt.num
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337 assert rt < 8
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338 assert self.offset % 4 == 0
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339 imm8 = self.offset >> 2
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340 assert imm8 < 256
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341 assert imm8 >= 0
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342 h = (0x9 << 11) | (rt << 8) | imm8
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343 return u16(h)
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344
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345 def __repr__(self):
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346 return 'LDR {}, {}'.format(self.rt, self.label.name)
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347
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348
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349 @instruction
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350 class Ldr1(ls_sp_base_imm8):
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351 """ ldr Rt, [SP, imm8] """
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352 mnemonic = 'LDR'
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353 opcode = 0x98
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354
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355
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356 @instruction
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357 class Str1(ls_sp_base_imm8):
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358 """ str Rt, [SP, imm8] """
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359 mnemonic = 'STR'
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360 opcode = 0x90
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361
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362
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363 @instruction
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364 class Mov3(ArmInstruction):
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365 """ mov Rd, imm8, move immediate value into register """
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366 mnemonic = 'mov'
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367 opcode = 4 # 00100 Rd(3) imm8
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368 operands = (Reg8Op, Imm8)
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369 def __init__(self, rd, imm):
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370 if type(imm) is int:
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371 imm = Imm8(imm)
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372 assert type(imm) is Imm8
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373 self.imm = imm.imm
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374 assert type(rd) is Reg8Op, str(type(rd))
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375 self.rd = rd
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376
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377 @classmethod
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378 def fromim(cls, im):
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379 return cls(im.dst[0], im.others[0])
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380
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381 def encode(self):
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382 rd = self.rd.num
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383 opcode = self.opcode
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384 imm8 = self.imm
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385 h = (opcode << 11) | (rd << 8) | imm8
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386 return u16(h)
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387
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388 def __repr__(self):
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389 return 'MOV {}, {}'.format(self.rd, self.imm)
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390
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391
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392
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393 # Arithmatics:
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394
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395
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396
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397 class regregimm3_base(ArmInstruction):
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398 operands = (Reg8Op, Reg8Op, Imm3)
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399 def __init__(self, rd, rn, imm3):
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400 self.rd = rd
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401 self.rn = rn
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402 assert type(imm3) is Imm3
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403 self.imm3 = imm3
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404
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405 @classmethod
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406 def fromim(cls, im):
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407 return cls(im.dst[0], im.src[0], im.others[0])
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408
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409 def encode(self):
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410 rd = self.rd.num
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411 rn = self.rn.num
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412 imm3 = self.imm3.imm
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413 opcode = self.opcode
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414 h = (self.opcode << 9) | (imm3 << 6) | (rn << 3) | rd
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415 return u16(h)
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416
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417 def __repr__(self):
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418 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.imm3.imm)
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419
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420 @instruction
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300
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421 class Add2(regregimm3_base):
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292
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422 """ add Rd, Rn, imm3 """
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423 mnemonic = 'add'
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424 opcode = 0b0001110
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425
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426
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427 @instruction
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300
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428 class Sub2(regregimm3_base):
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292
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429 """ sub Rd, Rn, imm3 """
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430 mnemonic = 'sub'
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431 opcode = 0b0001111
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432
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433
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434 class regregreg_base(ArmInstruction):
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435 """ ??? Rd, Rn, Rm """
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436 operands = (Reg8Op, Reg8Op, Reg8Op)
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437 def __init__(self, rd, rn, rm):
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438 self.rd = rd
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439 self.rn = rn
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440 self.rm = rm
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441
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442 @classmethod
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443 def fromim(cls, im):
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444 return cls(im.dst[0], im.src[0], im.src[1])
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445
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446 def encode(self):
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447 rd = self.rd.num
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448 rn = self.rn.num
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449 rm = self.rm.num
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450 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd
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451 return u16(h)
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452
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453 def __repr__(self):
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454 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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455
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456
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457 @instruction
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458 class Add(regregreg_base):
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459 mnemonic = 'ADD'
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460 opcode = 0b0001100
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461
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462
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463 @instruction
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464 class Sub(regregreg_base):
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465 mnemonic = 'SUB'
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466 opcode = 0b0001101
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467
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468
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469 @instruction
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470 class Mov2(ArmInstruction):
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471 """ mov rd, rm """
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472 operands = (ArmRegister, ArmRegister)
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473 mnemonic = 'MOV'
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474 def __init__(self, rd, rm):
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475 self.rd = rd
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476 self.rm = rm
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477
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478 @classmethod
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479 def fromim(cls, im):
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480 return cls(im.dst[0], im.src[0])
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481
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482 def encode(self):
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483 Rd = self.rd.num & 0x7
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484 D = (self.rd.num >> 3) & 0x1
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485 Rm = self.rm.num
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486 opcode = 0b01000110
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487 return u16((opcode << 8) | (D << 7) |(Rm << 3) | Rd)
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488
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489 def __repr__(self):
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490 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm)
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491
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492
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493 @instruction
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300
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494 class Mul(ArmInstruction):
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292
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495 """ mul Rn, Rdm """
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496 operands = (Reg8Op, Reg8Op)
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497 mnemonic = 'MUL'
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498 def __init__(self, rn, rdm):
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499 self.rn = rn
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500 self.rdm = rdm
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501
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502 @classmethod
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503 def fromim(cls, im):
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504 assert im.src[1] is im.dst[0]
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505 return cls(im.src[0], im.dst[0])
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506
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507 def encode(self):
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508 rn = self.rn.num
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509 rdm = self.rdm.num
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510 opcode = 0b0100001101
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511 h = (opcode << 6) | (rn << 3) | rdm
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512 return u16(h)
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513
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514 def __repr__(self):
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515 return '{} {}, {}'.format(self.mnemonic, self.rn, self.rdm)
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516
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517
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518 class regreg_base(ArmInstruction):
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|
519 """ ??? Rdn, Rm """
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520 operands = (Reg8Op, Reg8Op)
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521 # TODO: integrate with the code gen interface:
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522 src = (0, 1)
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523 dst = (0,)
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524 def __init__(self, rdn, rm):
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525 self.rdn = rdn
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526 self.rm = rm
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527
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528 @classmethod
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|
529 def fromim(cls, im):
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|
530 return cls(im.src[0], im.src[1])
|
|
|
531
|
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|
532 def encode(self):
|
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|
533 rdn = self.rdn.num
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|
534 rm = self.rm.num
|
|
|
535 h = (self.opcode << 6) | (rm << 3) | rdn
|
|
|
536 return u16(h)
|
|
|
537
|
|
|
538 def __repr__(self):
|
|
|
539 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
|
|
|
540
|
|
|
541
|
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|
542 @instruction
|
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543 class movregreg_ins(regreg_base):
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|
544 """ mov Rd, Rm (reg8 operands) """
|
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|
545 mnemonic = 'mov'
|
|
|
546 opcode = 0
|
|
|
547
|
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548
|
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549 @instruction
|
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|
550 class And(regreg_base):
|
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|
551 mnemonic = 'AND'
|
|
|
552 opcode = 0b0100000000
|
|
|
553
|
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|
554
|
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555 @instruction
|
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556 class Orr(regreg_base):
|
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|
557 mnemonic = 'ORR'
|
|
|
558 opcode = 0b0100001100
|
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|
559
|
|
|
560
|
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|
561 @instruction
|
|
|
562 class Cmp(regreg_base):
|
|
|
563 mnemonic = 'CMP'
|
|
|
564 opcode = 0b0100001010
|
|
|
565
|
|
|
566
|
|
|
567 @instruction
|
|
|
568 class Lsl(regreg_base):
|
|
|
569 mnemonic = 'LSL'
|
|
|
570 opcode = 0b0100000010
|
|
|
571
|
|
|
572
|
|
|
573 @instruction
|
|
|
574 class cmpregimm8_ins(ArmInstruction):
|
|
|
575 """ cmp Rn, imm8 """
|
|
|
576 mnemonic = 'cmp'
|
|
|
577 opcode = 5 # 00101
|
|
|
578 operands = (Reg8Op, Imm8)
|
|
|
579 def __init__(self, rn, imm):
|
|
|
580 self.rn = rn
|
|
|
581 self.imm = imm
|
|
|
582
|
|
|
583 def encode(self):
|
|
|
584 rn = self.rn.num
|
|
|
585 imm = self.imm.imm
|
|
|
586 opcode = self.opcode
|
|
|
587 h = (opcode << 11) | (rn << 8) | imm
|
|
|
588 return u16(h)
|
|
|
589
|
|
|
590
|
|
|
591 # Jumping:
|
|
|
592
|
|
|
593 def wrap_negative(x, bits):
|
|
|
594 b = struct.unpack('<I', struct.pack('<i', x))[0]
|
|
|
595 mask = (1 << bits) - 1
|
|
|
596 return b & mask
|
|
|
597
|
|
|
598 class jumpBase_ins(ArmInstruction):
|
|
|
599 operands = (LabelRef,)
|
|
|
600 def __init__(self, target_label):
|
|
|
601 assert type(target_label) is LabelRef
|
|
|
602 self.target = target_label
|
|
|
603 self.offset = 0
|
|
|
604
|
|
|
605 def resolve(self, f):
|
|
|
606 la = f(self.target.name)
|
|
|
607 sa = self.address + 4
|
|
|
608 self.offset = (la - sa)
|
|
|
609
|
|
|
610 def __repr__(self):
|
|
|
611 return '{} {}'.format(self.mnemonic, self.target.name)
|
|
|
612
|
|
|
613
|
|
|
614 @instruction
|
|
|
615 class B(jumpBase_ins):
|
|
|
616 mnemonic = 'B'
|
|
|
617 def encode(self):
|
|
|
618 imm11 = wrap_negative(self.offset >> 1, 11)
|
|
|
619 h = (0b11100 << 11) | imm11 # | 1 # 1 to enable thumb mode
|
|
|
620 return u16(h)
|
|
|
621
|
|
|
622
|
|
|
623 @instruction
|
|
|
624 class Bl(jumpBase_ins):
|
|
|
625 mnemonic = 'BL'
|
|
|
626 def encode(self):
|
|
|
627 imm32 = wrap_negative(self.offset >> 1, 32)
|
|
|
628 imm11 = imm32 & 0x7FF
|
|
|
629 imm10 = (imm32 >> 11) & 0x3FF
|
|
|
630 j1 = 1 # TODO: what do these mean?
|
|
|
631 j2 = 1
|
|
|
632 s = (imm32 >> 24) & 0x1
|
|
|
633 h1 = (0b11110 << 11) | (s << 10) | imm10
|
|
|
634 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11
|
|
|
635 return u16(h1) + u16(h2)
|
|
|
636
|
|
|
637
|
|
|
638 class cond_base_ins(jumpBase_ins):
|
|
|
639 def encode(self):
|
|
|
640 imm8 = wrap_negative(self.offset >> 1, 8)
|
|
|
641 h = (0b1101 << 12) | (self.cond << 8) | imm8
|
|
|
642 return u16(h)
|
|
|
643
|
|
|
644
|
|
|
645 @instruction
|
|
|
646 class Beq(cond_base_ins):
|
|
|
647 mnemonic = 'beq'
|
|
|
648 cond = 0
|
|
|
649
|
|
|
650
|
|
|
651 @instruction
|
|
|
652 class Bne(cond_base_ins):
|
|
|
653 mnemonic = 'bne'
|
|
|
654 cond = 1
|
|
|
655
|
|
|
656
|
|
|
657 @instruction
|
|
|
658 class Blt(cond_base_ins):
|
|
|
659 mnemonic = 'blt'
|
|
|
660 cond = 0b1011
|
|
|
661
|
|
|
662
|
|
|
663 @instruction
|
|
|
664 class Bgt(cond_base_ins):
|
|
|
665 mnemonic = 'bgt'
|
|
|
666 cond = 0b1100
|
|
|
667
|
|
|
668
|
|
|
669 @instruction
|
|
|
670 class Push(ArmInstruction):
|
|
|
671 operands = (RegisterSet,)
|
|
|
672 mnemonic = 'push'
|
|
|
673
|
|
|
674 def __init__(self, regs):
|
|
|
675 if type(regs) is set:
|
|
|
676 regs = RegisterSet(regs)
|
|
|
677 assert (type(regs),) == self.operands, (type(regs),)
|
|
|
678 self.regs = regs
|
|
|
679
|
|
|
680 def __repr__(self):
|
|
|
681 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
|
|
|
682
|
|
|
683 def encode(self):
|
|
|
684 reg_list = 0
|
|
|
685 M = 0
|
|
|
686 for n in self.regs.registerNumbers():
|
|
|
687 if n < 8:
|
|
|
688 reg_list |= (1 << n)
|
|
|
689 elif n == 14:
|
|
|
690 M = 1
|
|
|
691 else:
|
|
|
692 raise NotImplementedError('not implemented for this register')
|
|
|
693 h = (0x5a << 9) | (M << 8) | reg_list
|
|
|
694 return u16(h)
|
|
|
695
|
|
|
696
|
|
|
697 @instruction
|
|
|
698 class Pop(ArmInstruction):
|
|
|
699 operands = (RegisterSet,)
|
|
|
700 mnemonic = 'pop'
|
|
|
701
|
|
|
702 def __init__(self, regs):
|
|
|
703 if type(regs) is set:
|
|
|
704 regs = RegisterSet(regs)
|
|
|
705 assert (type(regs),) == self.operands, (type(regs),)
|
|
|
706 self.regs = regs
|
|
|
707
|
|
|
708 def __repr__(self):
|
|
|
709 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
|
|
|
710
|
|
|
711 def encode(self):
|
|
|
712 reg_list = 0
|
|
|
713 P = 0
|
|
|
714 for n in self.regs.registerNumbers():
|
|
|
715 if n < 8:
|
|
|
716 reg_list |= (1 << n)
|
|
|
717 elif n == 15:
|
|
|
718 P = 1
|
|
|
719 else:
|
|
|
720 raise NotImplementedError('not implemented for this register')
|
|
|
721 h = (0x5E << 9) | (P << 8) | reg_list
|
|
|
722 return u16(h)
|
|
|
723
|
|
|
724
|
|
|
725 @instruction
|
|
|
726 class Yield(ArmInstruction):
|
|
|
727 operands = ()
|
|
|
728 mnemonic = 'yield'
|
|
|
729
|
|
|
730 def encode(self):
|
|
|
731 return u16(0xbf10)
|
|
|
732
|
|
|
733 # misc:
|
|
|
734
|
|
|
735 # add/sub SP:
|
|
|
736 class addspsp_base(ArmInstruction):
|
|
|
737 operands = (RegSpOp, RegSpOp, Imm7)
|
|
|
738 def __init__(self, _sp, _sp2, imm7):
|
|
|
739 self.imm7 = imm7.imm
|
|
|
740 assert self.imm7 % 4 == 0
|
|
|
741 self.imm7 >>= 2
|
|
|
742
|
|
|
743 def encode(self):
|
|
|
744 return u16((self.opcode << 7) |self.imm7)
|
|
|
745
|
|
|
746 def __repr__(self):
|
|
|
747 return '{} sp, sp, {}'.format(self.mnemonic, self.imm7 << 2)
|
|
|
748
|
|
305
|
749
|
|
292
|
750 @instruction
|
|
|
751 class AddSp(addspsp_base):
|
|
|
752 mnemonic = 'add'
|
|
|
753 opcode = 0b101100000
|
|
|
754
|
|
|
755
|
|
|
756 @instruction
|
|
|
757 class SubSp(addspsp_base):
|
|
|
758 mnemonic = 'sub'
|
|
|
759 opcode = 0b101100001
|
