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1
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2 # Implementation of the ADI (ARM Debug Interface) v5 interface.
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3
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4 COMPONENT_CLASSES = {0x1: 'ROM table'}
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5
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6 class Adi:
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7 def __init__(self, iface):
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8 self.iface = iface
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9 def r32(self, address):
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10 return self.iface.read_debug32(address)
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11 def w32(self, address, value):
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12 self.iface.write_debug32(address, value)
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13 def getId(self, offset):
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14 print('reading id from {0:X}'.format(offset))
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15 pid4 = self.r32(offset + 0xFD0)
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16 #print('pid4', pid4)
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17 pid5 = self.r32(offset + 0xFD4)
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18 pid6 = self.r32(offset + 0xFD8)
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19 pid7 = self.r32(offset + 0xFDC)
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20 pid0 = self.r32(offset + 0xFE0)
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21 pid1 = self.r32(offset + 0xFE4)
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22 pid2 = self.r32(offset + 0xFE8)
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23 pid3 = self.r32(offset + 0xFEC)
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24 cid0 = self.r32(offset + 0xFF0)
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25 cid1 = self.r32(offset + 0xFF4)
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26 cid2 = self.r32(offset + 0xFF8)
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27 cid3 = self.r32(offset + 0xFFC)
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28 pids = [pid0, pid1, pid2, pid3, pid4, pid5, pid6, pid7]
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29 cids = [cid0, cid1, cid2, cid3]
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30 print('cids:', [hex(x) for x in cids], 'pids', [hex(x) for x in pids])
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31 valid = cid0 == 0xD and (cid1 & 0xF) == 0x0 and cid2 == 0x5 and cid3 == 0xB1
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32 if valid:
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33 component_class = cid1 >> 4
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34 else:
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35 print('invalid class')
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36 component_class = 0
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37 # TODO: use pids
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38 return component_class, pids
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39
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40 def parseRomTable(self, offset):
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41 assert (offset & 0xFFF) == 0
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42 component_class, pid = self.getId(offset)
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43 assert component_class == 1
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44 print('Component class:', COMPONENT_CLASSES[component_class])
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45 print('memory also on this bus:', self.r32(offset + 0xFCC))
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46 idx = 0
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47 entry = self.r32(offset + idx * 4)
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48 while entry != 0:
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49 #print('Entry: {0:X}'.format(entry))
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50 entryOffset = entry & 0xFFFFF000
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51 cls, pids = self.getId((offset + entryOffset) & 0xFFFFFFFF)
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52 print('class:', cls)
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53 if cls == 9:
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54 print('Debug block found!')
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55
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56 idx += 1
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57 entry = self.r32(offset + idx * 4)
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58
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59
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