|
292
|
1 import unittest
|
|
342
|
2 from ppci.outstream import BinaryOutputStream
|
|
335
|
3 from ppci.objectfile import ObjectFile
|
|
292
|
4 from asm import Assembler
|
|
|
5 from testasm import AsmTestCaseBase
|
|
345
|
6 from ppci.target.target_list import arm_target
|
|
292
|
7
|
|
|
8
|
|
346
|
9 a = Assembler(arm_target)
|
|
292
|
10
|
|
345
|
11 class ArmAssemblerTestCase(AsmTestCaseBase):
|
|
340
|
12 """ ARM-mode (not thumb-mode) instruction assembly test case """
|
|
|
13 def setUp(self):
|
|
341
|
14 self.t = arm_target
|
|
340
|
15 self.obj = ObjectFile()
|
|
346
|
16 self.ostream = BinaryOutputStream(self.obj)
|
|
348
|
17 self.ostream.select_section('.text')
|
|
346
|
18 self.a = a #Assembler(target=self.t)
|
|
340
|
19
|
|
|
20 def testMovImm(self):
|
|
|
21 self.feed('mov r4, 100')
|
|
|
22 self.check('6440a0e3')
|
|
345
|
23
|
|
346
|
24 def testMovImm2(self):
|
|
|
25 self.feed('mov sp, 0x6000')
|
|
|
26 self.check('06daa0e3')
|
|
|
27
|
|
362
|
28 def testMovReg(self):
|
|
|
29 self.feed('mov r3, sp')
|
|
|
30 self.feed('mov pc, lr')
|
|
|
31 self.feed('mov pc, r2')
|
|
|
32 self.feed('mov sp, r4')
|
|
|
33 self.feed('mov r5, r6')
|
|
|
34 self.check('0d30a0e1 0ef0a0e1 02f0a0e1 04d0a0e1 0650a0e1')
|
|
|
35
|
|
345
|
36 def testAdd2(self):
|
|
|
37 self.feed('add r12, r11, 300')
|
|
|
38 self.check('4bcf8be2')
|
|
|
39
|
|
|
40 def testAdd1(self):
|
|
|
41 self.feed('add r9, r7, r2')
|
|
|
42 self.check('029087e0')
|
|
|
43
|
|
|
44 def testSub1(self):
|
|
|
45 self.feed('sub r5, r6, r2')
|
|
|
46 self.check('025046e0')
|
|
|
47
|
|
|
48 def testSub2(self):
|
|
|
49 self.feed('sub r0, r1, 0x80000001')
|
|
|
50 self.check('060141e2')
|
|
|
51
|
|
356
|
52 def testAnd1(self):
|
|
|
53 self.feed('and r9, r0, r2')
|
|
|
54 self.feed('and r4, r8, r6')
|
|
|
55 self.check('029000e0 064008e0')
|
|
|
56
|
|
345
|
57 def testOrr1(self):
|
|
|
58 self.feed('orr r8, r7, r6')
|
|
|
59 self.check('068087e1')
|
|
|
60
|
|
356
|
61 def testLsl(self):
|
|
|
62 self.feed('lsl r11, r5, r3')
|
|
|
63 self.feed('lsl r4, r8, r6')
|
|
|
64 self.check('15b3a0e1 1846a0e1')
|
|
|
65
|
|
|
66 def testLsr(self):
|
|
|
67 self.feed('lsr r9, r0, r2')
|
|
|
68 self.feed('lsr r4, r8, r6')
|
|
|
69 self.check('3092a0e1 3846a0e1')
|
|
|
70
|
|
345
|
71 def testBranches(self):
|
|
|
72 self.feed('b sjakie')
|
|
|
73 self.feed('ble sjakie')
|
|
|
74 self.feed('bgt sjakie')
|
|
|
75 self.feed('beq sjakie')
|
|
|
76 self.feed('bl sjakie')
|
|
|
77 self.feed('sjakie:')
|
|
|
78 self.feed('b sjakie')
|
|
|
79 self.feed('ble sjakie')
|
|
|
80 self.feed('bgt sjakie')
|
|
|
81 self.feed('beq sjakie')
|
|
|
82 self.feed('bl sjakie')
|
|
|
83 self.check('030000ea 020000da 010000ca 0000000a ffffffeb feffffea fdffffda fcffffca fbffff0a faffffeb')
|
|
346
|
84
|
|
|
85 def testPush(self):
|
|
|
86 self.feed('push {r11,r5,r4,lr}')
|
|
|
87 self.check('30482de9')
|
|
|
88
|
|
|
89 def testPop(self):
|
|
|
90 self.feed('pop {r4,r5,r6}')
|
|
|
91 self.check('7000bde8')
|
|
|
92
|
|
|
93 def testStr(self):
|
|
|
94 self.feed('str r9, [r2, 33]')
|
|
|
95 self.check('219082e5')
|
|
|
96
|
|
|
97 def testLdr(self):
|
|
|
98 self.feed('ldr r5, [r3, 87]')
|
|
|
99 self.check('575093e5')
|
|
|
100
|
|
349
|
101 def testLdrLabel(self):
|
|
|
102 self.feed('ldr r5, lab1')
|
|
|
103 self.feed('ldr r11, lab1')
|
|
|
104 self.feed('ldr r10, lab1')
|
|
|
105 self.feed('lab1:')
|
|
|
106 self.feed('dcd 0x12345566')
|
|
|
107 self.check('04509fe5 00b09fe5 04a01fe5 66553412')
|
|
|
108
|
|
352
|
109 def testCmp(self):
|
|
|
110 self.feed('cmp r4, r11')
|
|
|
111 self.feed('cmp r5, 0x50000')
|
|
|
112 self.check('0b0054e1 050855e3')
|
|
|
113
|
|
346
|
114 def testSequence1(self):
|
|
|
115 self.feed('sub r4,r5,23')
|
|
|
116 self.feed('blt x')
|
|
|
117 self.feed('x:')
|
|
|
118 self.feed('mul r4,r5,r2')
|
|
|
119 self.check('174045e2 ffffffba 950204e0')
|
|
|
120
|
|
354
|
121 def testAdr(self):
|
|
|
122 self.feed('adr r5, cval')
|
|
|
123 self.feed('adr r9, cval')
|
|
|
124 self.feed('adr r8, cval')
|
|
|
125 self.feed('cval:')
|
|
|
126 self.feed('adr r11, cval')
|
|
|
127 self.feed('adr r12, cval')
|
|
|
128 self.feed('adr r1, cval')
|
|
|
129 self.check('04508fe2 00908fe2 04804fe2 08b04fe2 0cc04fe2 10104fe2')
|
|
|
130
|
|
362
|
131 def testMcr(self):
|
|
|
132 """ Test move coprocessor register from arm register """
|
|
|
133 self.feed('mcr p15, 0, r1, c2, c0, 0')
|
|
|
134 self.feed('mcr p14, 0, r1, c8, c7, 0')
|
|
|
135 self.check('101f02ee 171e08ee')
|
|
|
136
|
|
|
137 def testMrc(self):
|
|
|
138 self.feed('mrc p15, 0, r1, c2, c0, 0')
|
|
|
139 self.feed('mrc p14, 0, r1, c8, c7, 0')
|
|
|
140 self.check('101f12ee 171e18ee')
|
|
|
141
|
|
346
|
142
|
|
|
143 if __name__ == '__main__':
|
|
|
144 unittest.main()
|
