diff test/testarmasm.py @ 345:b4882ff0ed06

Added more arm isa tests
author Windel Bouwman
date Sun, 02 Mar 2014 17:12:08 +0100
parents 86b02c98a717
children 3bb7dcfe5529
line wrap: on
line diff
--- a/test/testarmasm.py	Sat Mar 01 16:32:27 2014 +0100
+++ b/test/testarmasm.py	Sun Mar 02 17:12:08 2014 +0100
@@ -3,152 +3,11 @@
 from ppci.objectfile import ObjectFile
 from asm import Assembler
 from testasm import AsmTestCaseBase
-from ppci.target.target_list import arm_target, thumb_target
+from ppci.target.target_list import arm_target
 
 
-class ThumbAssemblerTestCase(AsmTestCaseBase):
-    def setUp(self):
-        self.t = thumb_target
-        self.obj = ObjectFile()
-        self.o = BinaryOutputStream(self.obj)
-        self.o.selectSection('.text')
-        self.a = Assembler(target=self.t, stream=self.o)
 
-    def testMovImm8(self):
-        self.feed('mov r4, 100')
-        self.check('6424')
-
-    @unittest.skip
-    def testMovExt(self):
-        self.feed('mov r3, sp')
-        self.check('')
-
-    def testYield(self):
-        self.feed('yield')
-        self.check('10bf')
-
-    def testPush(self):
-        self.feed('push {r2,r3,lr}')
-        self.check('0cb5')
-
-    def testPop(self):
-        self.feed('pop {r4-r6, pc}')
-        self.check('70bd')
-
-    def testStr5(self):
-        self.feed('str r4, [r1 + 0]')
-        self.check('0c60')
-
-    def testLdr5(self):
-        self.feed('ldr r4, [r0 + 0]')
-        self.check('0468')
-
-    def testLdrSpRel(self):
-        self.feed('ldr r0, [sp + 4]')
-        self.check('0198')
-
-    def testStrSpRel(self):
-        self.feed('str r0, [sp + 4]')
-        self.check('0190')
-
-    def testLdrPcRel(self):
-        self.feed('ldr r7, henkie')
-        self.feed('ldr r6, henkie')
-        self.feed('ldr r1, henkie')
-        self.feed('align 4')
-        self.feed('dcd 1')
-        self.feed('henkie: dcd 2')
-        self.check('024F024E 01490000 01000000 02000000')
-
-    def testBranch(self):
-        self.feed('start: b henkie')
-        self.feed('beq henkie')
-        self.feed('bne henkie')
-        self.feed('henkie: b start')
-        self.feed('eof: b eof')
-        self.check('01e000d0 ffd1fbe7 fee7')
-
-    def testConditions(self):
-        self.feed('blt x')
-        self.feed('bgt x')
-        self.feed('x:')
-        self.check('00dbffdc')
-
-    def testBoff(self):
-        self.feed('b henkie')
-        self.feed('b henkie')
-        self.feed('b henkie')
-        self.feed('b henkie')
-        self.feed('b henkie')
-        self.feed('b henkie')
-        self.feed('b henkie')
-        self.feed('henkie:')
-        self.feed('b henkie')
-        self.feed('b henkie')
-        self.feed('b henkie')
-        self.feed('b henkie')
-        self.check('05e004e0 03e002e0 01e000e0 ffe7fee7 fde7fce7 fbe7')
-
-    def testBl(self):
-        self.feed('bl henkie')
-        self.feed('bl henkie')
-        self.feed('henkie:')
-        self.feed('bl henkie')
-        self.feed('bl henkie')
-        self.check('00f0 02f8 00f0 00f8 fff7 feff fff7 fcff')
-
-    def testCmpRegReg(self):
-        self.feed('cmp r0, r1')
-        self.check('8842')
-
-    def testAddimm3(self):
-        self.feed('add r3, r5, 2')
-        self.feed('add r4, r1, 6')
-        self.check('ab1c8c1d')
-
-    def testSubImm3(self):
-        self.feed('sub r3, r5, 2')
-        self.feed('sub r4, r1, 6')
-        self.check('ab1e8c1f')
-
-    def testLeftShift(self):
-        self.feed('lsl r3, r5')
-        self.check('ab40')
-
-    def testAddSp(self):
-        self.feed('add sp,sp,8')
-        self.feed('add sp,sp,16')
-        self.check('02b004b0')
-
-    def testSubSp(self):
-        self.feed('sub sp,sp,32')
-        self.feed('sub sp,sp,4')
-        self.check('88b081b0')
-
-    def testSequence1(self):
-        self.feed('mov r5, 3')
-        self.feed('add r4, r5, 0')
-        self.feed('loop: add r6, r4, 7')
-        self.feed('cmp r6, 5')
-        self.check('0325 2c1c e61d 052e')
-
-    def testSequence2(self):
-        self.feed('henkie:')
-        self.feed('push {r1,r4,r5}')
-        self.feed('add r5, r2, r4')
-        self.feed('cmp r4, r2')
-        self.feed('ldr r0, [sp + 4]')
-        self.feed('str r3, [sp + 16]')
-        self.feed('pop {r1, r4, r5}')
-        self.feed('lsl r3, r4')
-        self.feed('cmp r3, r5')
-        self.feed('beq henkie')
-        self.feed('bne henkie')
-        self.feed('b henkie')
-        self.check('32b41519 94420198 049332bc a340ab42 f6d0f5d1 f4e7')
-
-
-class AssemblerArmTestCase(AsmTestCaseBase):
+class ArmAssemblerTestCase(AsmTestCaseBase):
     """ ARM-mode (not thumb-mode) instruction assembly test case """
     def setUp(self):
         self.t = arm_target
@@ -160,3 +19,37 @@
     def testMovImm(self):
         self.feed('mov r4, 100')
         self.check('6440a0e3')
+
+    def testAdd2(self):
+        self.feed('add r12, r11, 300')
+        self.check('4bcf8be2')
+
+    def testAdd1(self):
+        self.feed('add r9, r7, r2')
+        self.check('029087e0')
+
+    def testSub1(self):
+        self.feed('sub r5, r6, r2')
+        self.check('025046e0')
+
+    def testSub2(self):
+        self.feed('sub r0, r1, 0x80000001')
+        self.check('060141e2')
+
+    def testOrr1(self):
+        self.feed('orr r8, r7, r6')
+        self.check('068087e1')
+
+    def testBranches(self):
+        self.feed('b sjakie')
+        self.feed('ble sjakie')
+        self.feed('bgt sjakie')
+        self.feed('beq sjakie')
+        self.feed('bl sjakie')
+        self.feed('sjakie:')
+        self.feed('b sjakie')
+        self.feed('ble sjakie')
+        self.feed('bgt sjakie')
+        self.feed('beq sjakie')
+        self.feed('bl sjakie')
+        self.check('030000ea 020000da 010000ca 0000000a ffffffeb feffffea fdffffda fcffffca fbffff0a faffffeb')