annotate python/ppci/target/thumb/instructions.py @ 342:86b02c98a717 devel

Moved target directory
author Windel Bouwman
date Sat, 01 Mar 2014 15:40:31 +0100
parents python/target/arminstructions.py@4d204f6f7d4e
children 3bb7dcfe5529
rev   line source
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1 from ..basetarget import Register, Instruction, Target, Label
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2 from ..basetarget import Imm32, Imm8, Imm7, Imm3
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3 from ..token import u16, u32
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4 from .armtoken import ThumbToken
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5 from ..arm.registers import R0, ArmRegister, SP
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6
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7
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8 # Instructions:
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9
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10 class ThumbInstruction(Instruction):
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11 pass
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12
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13
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14 class Dcd(ThumbInstruction):
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15 def __init__(self, expr):
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16 if isinstance(expr, Imm32):
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17 self.expr = expr.imm
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18 self.label = None
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19 elif isinstance(expr, int):
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20 self.expr = expr
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21 self.label = None
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22 else:
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23 raise NotImplementedError()
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24
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25 def encode(self):
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26 return u32(self.expr)
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27
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28 def relocations(self):
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29 return []
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30
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31 def __repr__(self):
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32 return 'DCD 0x{0:X}'.format(self.expr)
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33
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34
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35 class nop_ins(ThumbInstruction):
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36 def encode(self):
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37 return bytes()
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38
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39 def __repr__(self):
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40 return 'NOP'
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41
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42
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43 # Memory related
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44
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45 class LS_imm5_base(ThumbInstruction):
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46 """ ??? Rt, [Rn, imm5] """
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47 def __init__(self, rt, rn, imm5):
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48 assert imm5 % 4 == 0
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49 self.imm5 = imm5 >> 2
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50 self.rn = rn
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51 self.rt = rt
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52 assert self.rn.num < 8
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53 assert self.rt.num < 8
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54 self.token = ThumbToken()
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55
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56 def encode(self):
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57 Rn = self.rn.num
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58 Rt = self.rt.num
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59 imm5 = self.imm5
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60 self.token[0:3] = Rt
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61 self.token[3:6] = Rn
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62 self.token[6:11] = imm5
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63 self.token[11:16] = self.opcode
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64 return self.token.encode()
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65
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66 def __repr__(self):
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67 mnemonic = "???"
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68 return '{} {}, [{}, {}]'.format(mnemonic, self.rt, self.rn, self.imm5)
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69
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70
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71 class Str2(LS_imm5_base):
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72 opcode = 0xC
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73
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74 @classmethod
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75 def fromim(cls, im):
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76 return cls(im.src[1], im.src[0], im.others[0])
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77
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78
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79 class Ldr2(LS_imm5_base):
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80 opcode = 0xD
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81
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82 @classmethod
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83 def fromim(cls, im):
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84 return cls(im.dst[0], im.src[0], im.others[0])
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85
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86 class ls_sp_base_imm8(ThumbInstruction):
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87 def __init__(self, rt, offset):
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88 self.rt = rt
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89 self.offset = offset
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90
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91 def encode(self):
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92 rt = self.rt.num
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93 assert rt < 8
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94 imm8 = self.offset >> 2
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95 assert imm8 < 256
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96 h = (self.opcode << 8) | (rt << 8) | imm8
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97 return u16(h)
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98
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99 def __repr__(self):
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100 mnemonic = self.__class__.__name__
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101 return '{} {}, [sp,#{}]'.format(mnemonic, self.rt, self.offset)
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102
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103 def align(x, m):
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104 while ((x % m) != 0):
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105 x = x + 1
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106 return x
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107
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108 def Ldr(*args):
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109 if len(args) == 2 and isinstance(args[0], ArmRegister) \
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110 and isinstance(args[1], str):
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111 return Ldr3(*args)
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112 else:
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113 raise Exception()
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114
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115
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116 class Ldr3(ThumbInstruction):
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117 """ ldr Rt, LABEL, load value from pc relative position """
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118 mnemonic = 'ldr'
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119 def __init__(self, rt, label):
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120 self.rt = rt
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121 self.label = label
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122
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123 @classmethod
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124 def fromim(cls, im):
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125 return cls(im.dst[0], im.others[0])
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126
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127 def relocations(self):
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128 return [(self.label, 'lit_add_8')]
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129
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130 def encode(self):
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131 rt = self.rt.num
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132 assert rt < 8
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133 imm8 = 0
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134 h = (0x9 << 11) | (rt << 8) | imm8
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135 return u16(h)
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136
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137 def __repr__(self):
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138 return 'LDR {}, {}'.format(self.rt, self.label)
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139
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140
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141 class Ldr1(ls_sp_base_imm8):
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142 """ ldr Rt, [SP, imm8] """
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143 opcode = 0x98
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144
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145
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146 class Str1(ls_sp_base_imm8):
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147 """ str Rt, [SP, imm8] """
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148 opcode = 0x90
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149
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150
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151 class Mov3(ThumbInstruction):
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152 """ mov Rd, imm8, move immediate value into register """
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153 opcode = 4 # 00100 Rd(3) imm8
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154 def __init__(self, rd, imm):
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155 assert imm < 256
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156 self.imm = imm
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157 self.rd = rd
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158 self.token = ThumbToken()
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159
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160 @classmethod
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161 def fromim(cls, im):
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162 return cls(im.dst[0], im.others[0])
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163
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164 def encode(self):
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165 rd = self.rd.num
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166 self.token[8:11] = rd
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167 self.token[0:8] = self.imm
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168 self.token[11:16] = self.opcode
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169 return self.token.encode()
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170
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171 def __repr__(self):
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172 return 'MOV {}, {}'.format(self.rd, self.imm)
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173
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174
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175
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176 # Arithmatics:
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177
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178
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179
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180 class regregimm3_base(ThumbInstruction):
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181 def __init__(self, rd, rn, imm3):
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182 self.rd = rd
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183 self.rn = rn
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184 assert imm3 < 8
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185 self.imm3 = imm3
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186 self.token = ThumbToken()
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187
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188 @classmethod
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189 def fromim(cls, im):
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190 return cls(im.dst[0], im.src[0], im.others[0])
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191
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192 def encode(self):
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193 rd = self.rd.num
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194 self.token[0:3] = rd
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195 self.token[3:6] = self.rn.num
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196 self.token[6:9] = self.imm3
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197 self.token[9:16] = self.opcode
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198 return self.token.encode()
292
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199
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200 def __repr__(self):
341
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201 mnemonic = self.__class__.__name__
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202 return '{} {}, {}, {}'.format(mnemonic, self.rd, self.rn, self.imm3)
292
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203
340
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204
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205
300
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206 class Add2(regregimm3_base):
292
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207 """ add Rd, Rn, imm3 """
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208 opcode = 0b0001110
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209
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210
300
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211 class Sub2(regregimm3_base):
292
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212 """ sub Rd, Rn, imm3 """
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213 opcode = 0b0001111
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214
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215
341
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216 def Sub(*args):
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217 if len(args) == 3 and args[0] is SP and args[1] is SP and \
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218 isinstance(args[2], int) and args[2] < 256:
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219 return SubSp(args[2])
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220 elif len(args) == 3 and isinstance(args[0], ArmRegister) and \
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221 isinstance(args[1], ArmRegister) and isinstance(args[2], int) and \
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222 args[2] < 8:
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223 return Sub2(args[0], args[1], args[2])
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224 else:
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225 raise Exception()
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226
342
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227
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228 def Add(*args):
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229 if len(args) == 3 and args[0] is SP and args[1] is SP and \
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230 isinstance(args[2], int) and args[2] < 256:
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231 return AddSp(args[2])
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232 elif len(args) == 3 and isinstance(args[0], ArmRegister) and \
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233 isinstance(args[1], ArmRegister) and isinstance(args[2], int) and \
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234 args[2] < 8:
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235 return Add2(args[0], args[1], args[2])
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236 else:
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237 raise Exception()
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238
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239
341
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240 class regregreg_base(ThumbInstruction):
292
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241 """ ??? Rd, Rn, Rm """
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242 def __init__(self, rd, rn, rm):
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243 self.rd = rd
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244 self.rn = rn
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245 self.rm = rm
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246
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247 @classmethod
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248 def fromim(cls, im):
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249 return cls(im.dst[0], im.src[0], im.src[1])
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250
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251 def encode(self):
340
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252 at = ThumbToken()
336
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253 at.rd = self.rd.num
292
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254 rn = self.rn.num
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255 rm = self.rm.num
336
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256 at[3:6] = rn
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257 at[6:9] = rm
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258 at[9:16] = self.opcode
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259 return at.encode()
292
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260
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261 def __repr__(self):
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262 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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263
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264
341
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265 class Add3(regregreg_base):
292
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266 mnemonic = 'ADD'
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267 opcode = 0b0001100
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268
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269
341
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270 class Sub3(regregreg_base):
292
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271 mnemonic = 'SUB'
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272 opcode = 0b0001101
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273
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274
341
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275 class Mov2(ThumbInstruction):
292
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276 """ mov rd, rm """
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277 mnemonic = 'MOV'
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278 def __init__(self, rd, rm):
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279 self.rd = rd
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280 self.rm = rm
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281
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282 @classmethod
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283 def fromim(cls, im):
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284 return cls(im.dst[0], im.src[0])
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285
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286 def encode(self):
340
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287 at = ThumbToken()
336
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diff changeset
288 at.rd = self.rd.num & 0x7
292
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289 D = (self.rd.num >> 3) & 0x1
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290 Rm = self.rm.num
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291 opcode = 0b01000110
336
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292 at[8:16] = opcode
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293 at[3:7] = Rm
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294 at[7] = D
341
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diff changeset
295 return at.encode()
292
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296
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297 def __repr__(self):
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298 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm)
335
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diff changeset
299
292
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300
341
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diff changeset
301 class Mul(ThumbInstruction):
292
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302 """ mul Rn, Rdm """
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303 mnemonic = 'MUL'
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304 def __init__(self, rn, rdm):
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305 self.rn = rn
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306 self.rdm = rdm
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307
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308 @classmethod
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309 def fromim(cls, im):
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310 assert im.src[1] is im.dst[0]
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311 return cls(im.src[0], im.dst[0])
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312
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313 def encode(self):
340
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diff changeset
314 at = ThumbToken()
292
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315 rn = self.rn.num
336
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diff changeset
316 at.rd = self.rdm.num
292
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317 opcode = 0b0100001101
336
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diff changeset
318 #h = (opcode << 6) | (rn << 3) | rdm
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319 at[6:16] = opcode
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320 at[3:6] = rn
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321 return at.encode()
292
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322
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323 def __repr__(self):
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324 return '{} {}, {}'.format(self.mnemonic, self.rn, self.rdm)
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325
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326
341
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diff changeset
327 class regreg_base(ThumbInstruction):
292
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328 """ ??? Rdn, Rm """
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329 def __init__(self, rdn, rm):
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330 self.rdn = rdn
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331 self.rm = rm
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332
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333 @classmethod
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334 def fromim(cls, im):
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335 return cls(im.src[0], im.src[1])
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336
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337 def encode(self):
340
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diff changeset
338 at = ThumbToken()
336
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diff changeset
339 at.rd = self.rdn.num
292
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340 rm = self.rm.num
336
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diff changeset
341 at[3:6] = rm
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342 at[6:16] = self.opcode
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diff changeset
343 return at.encode()
292
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344
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345 def __repr__(self):
341
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diff changeset
346 mnemonic = self.__class__.__name__
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347 return '{} {}, {}'.format(mnemonic, self.rdn, self.rm)
292
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348
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349
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350 class movregreg_ins(regreg_base):
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diff changeset
351 """ mov Rd, Rm (reg8 operands) """
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diff changeset
352 opcode = 0
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353
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354
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355 class And(regreg_base):
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diff changeset
356 opcode = 0b0100000000
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357
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358
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359 class Orr(regreg_base):
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360 opcode = 0b0100001100
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361
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362
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363 class Cmp(regreg_base):
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364 opcode = 0b0100001010
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365
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366
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367 class Lsl(regreg_base):
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368 opcode = 0b0100000010
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diff changeset
369
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diff changeset
370
342
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diff changeset
371 class Cmp2(ThumbInstruction):
292
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parents:
diff changeset
372 """ cmp Rn, imm8 """
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373 opcode = 5 # 00101
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374 def __init__(self, rn, imm):
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375 self.rn = rn
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376 self.imm = imm
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377
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378 def encode(self):
341
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diff changeset
379 at = ThumbToken()
342
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diff changeset
380 at[0:8] = self.imm
341
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diff changeset
381 at[8:11] = self.rn.num
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diff changeset
382 at[11:16] = self.opcode
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383 return at.encode()
292
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384
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385
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386 # Jumping:
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387
341
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388 class jumpBase_ins(ThumbInstruction):
292
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389 def __init__(self, target_label):
342
86b02c98a717 Moved target directory
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390 assert type(target_label) is str
292
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391 self.target = target_label
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392 self.offset = 0
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393
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394 def __repr__(self):
341
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395 mnemonic = self.__class__.__name__
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396 return '{} {}'.format(mnemonic, self.target)
292
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397
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398
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399 class B(jumpBase_ins):
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400 def encode(self):
341
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401 h = (0b11100 << 11) | 0
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402 # | 1 # 1 to enable thumb mode
292
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403 return u16(h)
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404
335
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405 def relocations(self):
341
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406 return [(self.target, 'wrap_new11')]
292
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407
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408 class Bl(jumpBase_ins):
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409 def encode(self):
341
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410 imm11 = 0
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411 imm10 = 0
292
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412 j1 = 1 # TODO: what do these mean?
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413 j2 = 1
341
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414 s = 0
292
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415 h1 = (0b11110 << 11) | (s << 10) | imm10
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416 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11
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417 return u16(h1) + u16(h2)
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418
335
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419 def relocations(self):
341
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420 return [(self.target, 'bl_imm11_imm10')]
292
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421
335
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422
336
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423 class cond_base_ins(jumpBase_ins):
292
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424 def encode(self):
341
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425 imm8 = 0
292
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426 h = (0b1101 << 12) | (self.cond << 8) | imm8
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427 return u16(h)
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428
335
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429 def relocations(self):
341
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430 return [(self.target, 'rel8')]
335
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431
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432
336
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433 class cond_base_ins_long(jumpBase_ins):
335
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434 """ Encoding T3 """
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435 def encode(self):
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436 j1 = 1 # TODO: what do these mean?
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437 j2 = 1
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438 h1 = (0b11110 << 11) | (self.cond << 6)
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439 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11)
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440 return u16(h1) + u16(h2)
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441
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442 def relocations(self):
341
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443 return [(self.target, 'b_imm11_imm6')]
335
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444
292
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445
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446 class Beq(cond_base_ins):
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447 cond = 0
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448
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449
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450 class Bne(cond_base_ins):
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451 cond = 1
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452
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453
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454 class Blt(cond_base_ins):
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455 cond = 0b1011
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456
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457
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458 class Bgt(cond_base_ins):
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459 cond = 0b1100
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460
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461
341
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462 class Push(ThumbInstruction):
292
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463 def __init__(self, regs):
341
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diff changeset
464 assert type(regs) is set
292
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465 self.regs = regs
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466
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467 def __repr__(self):
341
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468 return 'Push {{{}}}'.format(self.regs)
292
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469
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470 def encode(self):
341
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diff changeset
471 at = ThumbToken()
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diff changeset
472 for n in register_numbers(self.regs):
292
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473 if n < 8:
341
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diff changeset
474 at[n] = 1
292
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475 elif n == 14:
341
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diff changeset
476 at[8] = 1
292
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477 else:
341
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diff changeset
478 raise NotImplementedError('not implemented for {}'.format(n))
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diff changeset
479 at[9:16] = 0x5a
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diff changeset
480 return at.encode()
4d204f6f7d4e Rewrite of assembler parts
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diff changeset
481
292
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482
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483
341
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diff changeset
484 def register_numbers(regs):
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diff changeset
485 for r in regs:
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486 yield r.num
340
c7cc54c0dfdf Test featurebranch
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diff changeset
487
341
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diff changeset
488 class Pop(ThumbInstruction):
292
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parents:
diff changeset
489 def __init__(self, regs):
341
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diff changeset
490 assert type(regs) is set
292
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491 self.regs = regs
341
4d204f6f7d4e Rewrite of assembler parts
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diff changeset
492 self.token = ThumbToken()
292
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parents:
diff changeset
493
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diff changeset
494 def __repr__(self):
341
4d204f6f7d4e Rewrite of assembler parts
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diff changeset
495 return 'Pop {{{}}}'.format(self.regs)
292
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
496
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diff changeset
497 def encode(self):
341
4d204f6f7d4e Rewrite of assembler parts
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diff changeset
498 for n in register_numbers(self.regs):
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
499 if n < 8:
341
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diff changeset
500 self.token[n] = 1
292
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
501 elif n == 15:
341
4d204f6f7d4e Rewrite of assembler parts
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diff changeset
502 self.token[8] = 1
292
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
503 else:
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parents:
diff changeset
504 raise NotImplementedError('not implemented for this register')
341
4d204f6f7d4e Rewrite of assembler parts
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parents: 340
diff changeset
505 self.token[9:16] = 0x5E
4d204f6f7d4e Rewrite of assembler parts
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diff changeset
506 return self.token.encode()
292
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
507
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
508
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
509
341
4d204f6f7d4e Rewrite of assembler parts
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diff changeset
510 class Yield(ThumbInstruction):
292
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parents:
diff changeset
511 def encode(self):
534b94b40aa8 Fixup reorganize
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diff changeset
512 return u16(0xbf10)
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
513
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parents:
diff changeset
514 # misc:
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
515
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parents:
diff changeset
516 # add/sub SP:
341
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diff changeset
517 class addspsp_base(ThumbInstruction):
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diff changeset
518 def __init__(self, imm7):
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diff changeset
519 self.imm7 = imm7
292
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parents:
diff changeset
520 assert self.imm7 % 4 == 0
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parents:
diff changeset
521 self.imm7 >>= 2
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diff changeset
522
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
523 def encode(self):
341
4d204f6f7d4e Rewrite of assembler parts
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parents: 340
diff changeset
524 return u16((self.opcode << 7) | self.imm7)
292
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parents:
diff changeset
525
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
526 def __repr__(self):
341
4d204f6f7d4e Rewrite of assembler parts
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parents: 340
diff changeset
527 mnemonic = self.__class__.__name__
4d204f6f7d4e Rewrite of assembler parts
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parents: 340
diff changeset
528 return '{} sp, sp, {}'.format(mnemonic, self.imm7 << 2)
292
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
529
305
0615b5308710 Updated docs
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diff changeset
530
292
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parents:
diff changeset
531 class AddSp(addspsp_base):
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parents:
diff changeset
532 opcode = 0b101100000
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parents:
diff changeset
533
534b94b40aa8 Fixup reorganize
Windel Bouwman
parents:
diff changeset
534
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
535 class SubSp(addspsp_base):
534b94b40aa8 Fixup reorganize
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parents:
diff changeset
536 opcode = 0b101100001