|
205
|
1 import struct, types
|
|
206
|
2 from target import Register, Instruction, Target, Imm8, Label, Imm3
|
|
219
|
3 from asmnodes import ASymbol, ANumber, AUnop, ABinop, ALabel
|
|
202
|
4 from ppci import CompilerError
|
|
205
|
5 import ir
|
|
202
|
6
|
|
218
|
7 # TODO: encode this in DSL (domain specific language)
|
|
|
8
|
|
202
|
9 def u16(h):
|
|
|
10 return struct.pack('<H', h)
|
|
|
11
|
|
205
|
12 def u32(x):
|
|
|
13 return struct.pack('<I', x)
|
|
|
14
|
|
202
|
15 armtarget = Target('arm')
|
|
|
16
|
|
|
17 class ArmReg(Register):
|
|
|
18 def __init__(self, num, name):
|
|
|
19 super().__init__(name)
|
|
|
20 self.num = num
|
|
206
|
21 def __repr__(self):
|
|
|
22 return self.name
|
|
202
|
23
|
|
203
|
24 class RegOp:
|
|
|
25 def __init__(self, num):
|
|
206
|
26 assert num < 16
|
|
203
|
27 self.num = num
|
|
|
28
|
|
|
29 @classmethod
|
|
|
30 def Create(cls, vop):
|
|
|
31 if type(vop) is ASymbol:
|
|
|
32 name = vop.name
|
|
|
33 regs = {}
|
|
|
34 for r in armtarget.registers:
|
|
|
35 regs[r.name] = r
|
|
|
36 if name in regs:
|
|
|
37 r = regs[name]
|
|
|
38 return cls(r.num)
|
|
219
|
39
|
|
|
40 class Reg8Op:
|
|
|
41 def __init__(self, num):
|
|
|
42 assert num < 8
|
|
|
43 self.num = num
|
|
|
44
|
|
|
45 @classmethod
|
|
|
46 def Create(cls, vop):
|
|
|
47 if type(vop) is ASymbol:
|
|
|
48 name = vop.name
|
|
|
49 regs = {}
|
|
|
50 for r in armtarget.registers:
|
|
|
51 regs[r.name] = r
|
|
|
52 if name in regs:
|
|
|
53 r = regs[name]
|
|
|
54 if r.num < 8:
|
|
|
55 return cls(r.num)
|
|
203
|
56
|
|
206
|
57 def getRegNum(n):
|
|
|
58 for r in armtarget.registers:
|
|
|
59 if r.num == n:
|
|
|
60 return r
|
|
203
|
61
|
|
206
|
62 def getRegisterRange(n1, n2):
|
|
|
63 regs = []
|
|
|
64 if n1.num < n2.num:
|
|
|
65 for n in range(n1.num, n2.num + 1):
|
|
|
66 r = getRegNum(n)
|
|
|
67 assert r
|
|
|
68 regs.append(r)
|
|
|
69 return regs
|
|
203
|
70
|
|
212
|
71 class MemoryOp:
|
|
|
72 def __init__(self, basereg, offset):
|
|
|
73 assert type(basereg) is ArmReg
|
|
|
74 self.basereg = basereg
|
|
|
75 self.offset = offset
|
|
|
76
|
|
219
|
77 def __repr__(self):
|
|
|
78 return '[{}, #{}]'.format(self.basereg, self.offset)
|
|
|
79
|
|
212
|
80 @classmethod
|
|
|
81 def Create(cls, vop):
|
|
|
82 if type(vop) is AUnop and vop.operation == '[]':
|
|
|
83 vop = vop.arg # descent
|
|
|
84 if type(vop) is ABinop:
|
|
|
85 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
|
|
|
86 offset = vop.arg2.number
|
|
|
87 basereg = RegOp.Create(vop.arg1)
|
|
|
88 if not basereg:
|
|
|
89 return
|
|
|
90 else:
|
|
|
91 return
|
|
|
92 elif type(vop) is ASymbol:
|
|
|
93 offset = 0
|
|
|
94 basereg = RegOp.Create(vop)
|
|
|
95 if not basereg:
|
|
|
96 return
|
|
|
97 else:
|
|
|
98 return
|
|
|
99 return cls(getRegNum(basereg.num), offset)
|
|
219
|
100
|
|
223
|
101 class MemSpRel:
|
|
|
102 def __init__(self, offset):
|
|
|
103 assert offset % 4 == 0
|
|
|
104 self.offset = offset
|
|
|
105
|
|
|
106 def __repr__(self):
|
|
|
107 return '[sp, #{}]'.format(self.offset)
|
|
|
108
|
|
|
109 @classmethod
|
|
|
110 def Create(cls, vop):
|
|
|
111 if type(vop) is AUnop and vop.operation == '[]':
|
|
|
112 vop = vop.arg # descent
|
|
|
113 if type(vop) is ABinop and vop.op == '+':
|
|
|
114 if type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber and vop.arg1.name.upper() == 'SP' and vop.arg2.number % 4 == 0:
|
|
|
115 offset = vop.arg2.number
|
|
|
116 return cls(offset)
|
|
|
117 elif type(vop) is ASymbol and vop.name.upper() == 'SP':
|
|
|
118 return cls(0)
|
|
|
119
|
|
219
|
120 class MemoryOpReg8Imm5:
|
|
|
121 def __init__(self, basereg, offset):
|
|
|
122 assert type(basereg) is ArmReg
|
|
|
123 self.basereg = basereg
|
|
|
124 self.offset = offset
|
|
|
125
|
|
|
126 def __repr__(self):
|
|
|
127 return '[{}, #{}]'.format(self.basereg, self.offset)
|
|
|
128
|
|
|
129 @classmethod
|
|
|
130 def Create(cls, vop):
|
|
|
131 if type(vop) is AUnop and vop.operation == '[]':
|
|
|
132 vop = vop.arg # descent
|
|
|
133 if type(vop) is ABinop:
|
|
|
134 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
|
|
|
135 offset = vop.arg2.number
|
|
|
136 if offset > 120:
|
|
|
137 return
|
|
|
138 basereg = Reg8Op.Create(vop.arg1)
|
|
|
139 if not basereg:
|
|
|
140 return
|
|
|
141 else:
|
|
|
142 return
|
|
|
143 elif type(vop) is ASymbol:
|
|
|
144 offset = 0
|
|
|
145 basereg = Reg8Op.Create(vop)
|
|
|
146 if not basereg:
|
|
|
147 return
|
|
|
148 else:
|
|
|
149 return
|
|
|
150 return cls(getRegNum(basereg.num), offset)
|
|
212
|
151
|
|
205
|
152 class RegisterSet:
|
|
|
153 def __init__(self, regs):
|
|
206
|
154 assert type(regs) is set
|
|
|
155 self.regs = regs
|
|
|
156 def __repr__(self):
|
|
|
157 return ','.join([str(r) for r in self.regs])
|
|
|
158 @classmethod
|
|
|
159 def Create(cls, vop):
|
|
|
160 assert type(vop) is AUnop and vop.operation == '{}'
|
|
|
161 assert type(vop.arg) is list
|
|
|
162 regs = set()
|
|
|
163 for arg in vop.arg:
|
|
|
164 if type(arg) is ASymbol:
|
|
|
165 reg = RegOp.Create(arg)
|
|
|
166 if not reg:
|
|
|
167 return
|
|
|
168 regs.add(reg)
|
|
|
169 elif type(arg) is ABinop and arg.op == '-':
|
|
|
170 reg1 = RegOp.Create(arg.arg1)
|
|
|
171 reg2 = RegOp.Create(arg.arg2)
|
|
|
172 if not reg1:
|
|
|
173 return
|
|
|
174 if not reg2:
|
|
|
175 return
|
|
|
176 for r in getRegisterRange(reg1, reg2):
|
|
|
177 regs.add(r)
|
|
|
178 else:
|
|
|
179 raise Exception('Cannot be')
|
|
|
180 return cls(regs)
|
|
|
181
|
|
|
182 def registerNumbers(self):
|
|
|
183 return [r.num for r in self.regs]
|
|
205
|
184
|
|
202
|
185 # 8 bit registers:
|
|
205
|
186 r0 = ArmReg(0, 'r0')
|
|
|
187 armtarget.registers.append(r0)
|
|
206
|
188 r1 = ArmReg(1, 'r1')
|
|
|
189 armtarget.registers.append(r1)
|
|
|
190 r2 = ArmReg(2, 'r2')
|
|
|
191 armtarget.registers.append(r2)
|
|
|
192 r3 = ArmReg(3, 'r3')
|
|
|
193 armtarget.registers.append(r3)
|
|
202
|
194 r4 = ArmReg(4, 'r4')
|
|
|
195 armtarget.registers.append(r4)
|
|
203
|
196 r5 = ArmReg(5, 'r5')
|
|
|
197 armtarget.registers.append(r5)
|
|
|
198 r6 = ArmReg(6, 'r6')
|
|
|
199 armtarget.registers.append(r6)
|
|
|
200 r7 = ArmReg(7, 'r7')
|
|
|
201 armtarget.registers.append(r7)
|
|
206
|
202 # Other registers:
|
|
|
203 # TODO
|
|
|
204 sp = ArmReg(13, 'sp')
|
|
|
205 armtarget.registers.append(sp)
|
|
|
206 lr = ArmReg(14, 'lr')
|
|
|
207 armtarget.registers.append(lr)
|
|
|
208 pc = ArmReg(15, 'pc')
|
|
|
209 armtarget.registers.append(pc)
|
|
202
|
210
|
|
|
211 class ArmInstruction(Instruction):
|
|
|
212 pass
|
|
|
213
|
|
205
|
214 class dcd_ins(ArmInstruction):
|
|
|
215 mnemonic = 'dcd'
|
|
|
216 def __init__(self, expr):
|
|
|
217 self.expr = expr
|
|
219
|
218
|
|
205
|
219 def encode(self):
|
|
|
220 return u32(self.expr)
|
|
202
|
221
|
|
219
|
222 def __repr__(self):
|
|
|
223 return 'DCD 0x{0:X}'.format(self.expr)
|
|
|
224
|
|
|
225
|
|
|
226
|
|
|
227 # Memory related
|
|
|
228
|
|
|
229 class LS_imm5_base(ArmInstruction):
|
|
|
230 """ ??? Rt, [Rn, imm5] """
|
|
|
231 operands = (Reg8Op, MemoryOpReg8Imm5)
|
|
212
|
232 def __init__(self, rt, memop):
|
|
|
233 assert memop.offset % 4 == 0
|
|
|
234 self.imm5 = memop.offset >> 2
|
|
|
235 self.rn = memop.basereg.num
|
|
|
236 self.rt = rt.num
|
|
219
|
237 self.memloc = memop
|
|
|
238 assert self.rn < 8
|
|
|
239 assert self.rt < 8
|
|
212
|
240
|
|
|
241 def encode(self):
|
|
|
242 Rn = self.rn
|
|
|
243 Rt = self.rt
|
|
|
244 imm5 = self.imm5
|
|
219
|
245
|
|
|
246 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
|
|
|
247 return u16(h)
|
|
|
248 def __repr__(self):
|
|
|
249 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
|
|
|
250
|
|
|
251 @armtarget.instruction
|
|
|
252 class storeimm5_ins(LS_imm5_base):
|
|
|
253 mnemonic = 'STR'
|
|
|
254 opcode = 0xC
|
|
|
255
|
|
|
256 @armtarget.instruction
|
|
|
257 class loadimm5_ins(LS_imm5_base):
|
|
|
258 mnemonic = 'LDR'
|
|
|
259 opcode = 0xD
|
|
|
260
|
|
|
261 class ls_sp_base_imm8(ArmInstruction):
|
|
|
262 operands = (Reg8Op, MemoryOp)
|
|
|
263 def __init__(self, rt, memop):
|
|
|
264 self.rt = rt
|
|
|
265 assert memop.basereg.num == 13
|
|
|
266 self.offset = memop.offset
|
|
|
267
|
|
|
268 def encode(self):
|
|
|
269 rt = self.rt.num
|
|
|
270 assert rt < 8
|
|
|
271 imm8 = self.offset >> 2
|
|
|
272 assert imm8 < 256
|
|
|
273 h = (self.opcode << 8) | (rt << 8) | imm8
|
|
212
|
274 return u16(h)
|
|
|
275
|
|
219
|
276 def __repr__(self):
|
|
|
277 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset)
|
|
|
278
|
|
212
|
279 @armtarget.instruction
|
|
219
|
280 class ldr_pcrel(ArmInstruction):
|
|
|
281 """ ldr Rt, [PC, imm8], store value into memory """
|
|
212
|
282 mnemonic = 'ldr'
|
|
|
283 operands = (RegOp, MemoryOp)
|
|
219
|
284 def __init__(self, rt, label):
|
|
|
285 self.rt = rt
|
|
|
286 self.label = label
|
|
|
287 self.offset = 0
|
|
212
|
288
|
|
|
289 def encode(self):
|
|
219
|
290 rt = self.rt.num
|
|
|
291 assert rt < 8
|
|
|
292 imm8 = self.offset >> 2
|
|
|
293 assert imm8 < 256
|
|
|
294 h = (0x9 << 11) | (rt << 8) | imm8
|
|
212
|
295 return u16(h)
|
|
|
296
|
|
219
|
297 def __repr__(self):
|
|
|
298 return 'LDR {}, [pc,#{}]'.format(self.rt, self.offset)
|
|
|
299
|
|
|
300 @armtarget.instruction
|
|
|
301 class ldr_sprel(ls_sp_base_imm8):
|
|
|
302 """ ldr Rt, [SP, imm8] """
|
|
|
303 mnemonic = 'LDR'
|
|
|
304 opcode = 0x98
|
|
|
305
|
|
|
306 @armtarget.instruction
|
|
|
307 class str_sprel(ls_sp_base_imm8):
|
|
|
308 """ str Rt, [SP, imm8] """
|
|
|
309 mnemonic = 'STR'
|
|
|
310 opcode = 0x90
|
|
|
311
|
|
212
|
312 @armtarget.instruction
|
|
202
|
313 class mov_ins(ArmInstruction):
|
|
|
314 """ mov Rd, imm8, move immediate value into register """
|
|
|
315 mnemonic = 'mov'
|
|
203
|
316 opcode = 4 # 00100 Rd(3) imm8
|
|
|
317 operands = (RegOp, Imm8)
|
|
205
|
318 irpattern = ir.ImmLoad
|
|
203
|
319 def __init__(self, rd, imm):
|
|
|
320 self.imm = imm.imm
|
|
|
321 self.r = rd.num
|
|
205
|
322
|
|
202
|
323 def encode(self):
|
|
|
324 rd = self.r
|
|
|
325 opcode = self.opcode
|
|
|
326 imm8 = self.imm
|
|
|
327 h = (opcode << 11) | (rd << 8) | imm8
|
|
|
328 return u16(h)
|
|
219
|
329 def __repr__(self):
|
|
|
330 return 'MOV {0}, xx?'.format(self.r)
|
|
202
|
331
|
|
203
|
332 @armtarget.instruction
|
|
|
333 class movregreg_ins(ArmInstruction):
|
|
|
334 """ mov Rd, Rm """
|
|
|
335 mnemonic = 'mov'
|
|
|
336 operands = (RegOp, RegOp)
|
|
|
337 def __init__(self, rd, rm):
|
|
|
338 self.rd = rd
|
|
|
339 self.rm = rm
|
|
|
340 def encode(self):
|
|
|
341 rd = self.rd.num
|
|
|
342 D = (rd & 0x8) >> 3
|
|
|
343 assert D < 2
|
|
|
344 rd = rd & 0x7
|
|
|
345 rm = self.rm.num
|
|
|
346 assert rm < 16
|
|
|
347 opcode = self.opcode
|
|
219
|
348 h = (1 << 14) | (3 << 9) | (D << 7) | (rm << 3) | rd
|
|
203
|
349 return u16(h)
|
|
|
350
|
|
219
|
351
|
|
|
352
|
|
|
353 # Arithmatics:
|
|
|
354
|
|
203
|
355 @armtarget.instruction
|
|
|
356 class addregregimm3_ins(ArmInstruction):
|
|
|
357 """ add Rd, Rn, imm3 """
|
|
|
358 mnemonic = 'add'
|
|
|
359 opcode = 3 # 00011
|
|
|
360 operands = (RegOp, RegOp, Imm3)
|
|
205
|
361 irpattern = 3
|
|
203
|
362 def __init__(self, rd, rn, imm3):
|
|
|
363 self.rd = rd
|
|
|
364 self.rn = rn
|
|
|
365 self.imm3 = imm3
|
|
|
366 def encode(self):
|
|
|
367 rd = self.rd.num
|
|
|
368 rn = self.rn.num
|
|
|
369 imm3 = self.imm3.imm
|
|
|
370 opcode = self.opcode
|
|
|
371 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd
|
|
|
372 return u16(h)
|
|
|
373
|
|
219
|
374 class regregreg_base(ArmInstruction):
|
|
|
375 """ ??? Rd, Rn, Rm """
|
|
|
376 operands = (Reg8Op, Reg8Op, Reg8Op)
|
|
|
377 def __init__(self, rd, rn, rm):
|
|
|
378 self.rd = rd
|
|
|
379 self.rn = rn
|
|
|
380 self.rm = rm
|
|
|
381 def encode(self):
|
|
|
382 rd = self.rd.num
|
|
|
383 rn = self.rn.num
|
|
|
384 rm = self.rm.num
|
|
|
385 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd
|
|
|
386 return u16(h)
|
|
|
387 def __repr__(self):
|
|
|
388 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
|
|
|
389
|
|
|
390 @armtarget.instruction
|
|
|
391 class addregs_ins(regregreg_base):
|
|
|
392 mnemonic = 'ADD'
|
|
|
393 opcode = 0b0001100
|
|
|
394
|
|
|
395 @armtarget.instruction
|
|
|
396 class subregs_ins(regregreg_base):
|
|
|
397 mnemonic = 'SUB'
|
|
|
398 opcode = 0b0001101
|
|
|
399
|
|
|
400 class regreg_base(ArmInstruction):
|
|
|
401 """ ??? Rdn, Rm """
|
|
|
402 operands = (Reg8Op, Reg8Op)
|
|
|
403 def __init__(self, rdn, rm):
|
|
|
404 self.rdn = rdn
|
|
|
405 self.rm = rm
|
|
|
406 def encode(self):
|
|
|
407 rdn = self.rdn.num
|
|
|
408 rm = self.rm.num
|
|
|
409 h = (self.opcode << 6) | (rm << 3) | rdn
|
|
|
410 return u16(h)
|
|
|
411 def __repr__(self):
|
|
|
412 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
|
|
|
413
|
|
|
414 @armtarget.instruction
|
|
|
415 class andregs_ins(regreg_base):
|
|
|
416 mnemonic = 'AND'
|
|
|
417 opcode = 0b0100000000
|
|
|
418
|
|
|
419 @armtarget.instruction
|
|
|
420 class orrregs_ins(regreg_base):
|
|
|
421 mnemonic = 'ORR'
|
|
|
422 opcode = 0b0100001100
|
|
|
423
|
|
|
424 @armtarget.instruction
|
|
|
425 class cmp_ins(regreg_base):
|
|
|
426 mnemonic = 'CMP'
|
|
|
427 opcode = 0b0100001010
|
|
|
428
|
|
203
|
429 @armtarget.instruction
|
|
|
430 class cmpregimm8_ins(ArmInstruction):
|
|
|
431 """ cmp Rn, imm8 """
|
|
|
432 mnemonic = 'cmp'
|
|
|
433 opcode = 5 # 00101
|
|
|
434 operands = (RegOp, Imm8)
|
|
|
435 def __init__(self, rn, imm):
|
|
|
436 self.rn = rn
|
|
|
437 self.imm = imm
|
|
|
438 def encode(self):
|
|
|
439 rn = self.rn.num
|
|
|
440 imm = self.imm.imm
|
|
|
441 opcode = self.opcode
|
|
|
442 h = (opcode << 11) | (rn << 8) | imm
|
|
|
443 return u16(h)
|
|
202
|
444
|
|
219
|
445 # Jumping:
|
|
218
|
446
|
|
|
447 @armtarget.instruction
|
|
205
|
448 class jmp_ins(ArmInstruction):
|
|
219
|
449 operands = (ALabel,)
|
|
205
|
450 mnemonic = 'jmp'
|
|
|
451 def __init__(self, target_label):
|
|
219
|
452 assert type(target_label) is ALabel
|
|
205
|
453 self.target = target_label
|
|
|
454 def fixUp(self):
|
|
|
455 pass
|
|
|
456 def encode(self):
|
|
219
|
457 h = 0 # TODO
|
|
205
|
458 return u16(h)
|
|
219
|
459 def __repr__(self):
|
|
|
460 return 'B {0}'.format(self.target.name)
|
|
|
461
|
|
|
462 @armtarget.instruction
|
|
|
463 class beq_ins(ArmInstruction):
|
|
|
464 operands = (ALabel,)
|
|
|
465 mnemonic = 'beq'
|
|
|
466 def __init__(self, target_label):
|
|
|
467 assert type(target_label) is ALabel
|
|
|
468 self.target = target_label
|
|
|
469 def fixUp(self):
|
|
|
470 pass
|
|
|
471 def encode(self):
|
|
|
472 h = 0 # TODO
|
|
|
473 return u16(h)
|
|
|
474 def __repr__(self):
|
|
|
475 return 'BEQ {0}'.format(self.target.name)
|
|
205
|
476
|
|
|
477 @armtarget.instruction
|
|
|
478 class push_ins(ArmInstruction):
|
|
206
|
479 operands = (RegisterSet,)
|
|
205
|
480 mnemonic = 'push'
|
|
|
481 def __init__(self, regs):
|
|
206
|
482 assert (type(regs),) == self.operands, (type(regs),)
|
|
205
|
483 self.regs = regs
|
|
206
|
484 def __repr__(self):
|
|
|
485 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
|
|
205
|
486 def encode(self):
|
|
206
|
487 reg_list = 0
|
|
|
488 M = 0
|
|
|
489 for n in self.regs.registerNumbers():
|
|
|
490 if n < 8:
|
|
|
491 reg_list |= (1 << n)
|
|
|
492 elif n == 14:
|
|
|
493 M = 1
|
|
|
494 else:
|
|
|
495 raise NotImplementedError('not implemented for this register')
|
|
|
496 h = (0x5a << 9) | (M << 8) | reg_list
|
|
|
497 return u16(h)
|
|
205
|
498
|
|
|
499 @armtarget.instruction
|
|
|
500 class pop_ins(ArmInstruction):
|
|
206
|
501 operands = (RegisterSet,)
|
|
205
|
502 mnemonic = 'pop'
|
|
|
503 def __init__(self, regs):
|
|
|
504 self.regs = regs
|
|
207
|
505 def __repr__(self):
|
|
|
506 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
|
|
205
|
507 def encode(self):
|
|
206
|
508 reg_list = 0
|
|
|
509 P = 0
|
|
|
510 for n in self.regs.registerNumbers():
|
|
|
511 if n < 8:
|
|
|
512 reg_list |= (1 << n)
|
|
|
513 elif n == 15:
|
|
|
514 P = 1
|
|
|
515 else:
|
|
|
516 raise NotImplementedError('not implemented for this register')
|
|
|
517 h = (0x5E << 9) | (P << 8) | reg_list
|
|
|
518 return u16(h)
|
|
205
|
519
|
|
|
520 @armtarget.instruction
|
|
202
|
521 class yield_ins(ArmInstruction):
|
|
|
522 operands = ()
|
|
|
523 mnemonic = 'yield'
|
|
|
524 def encode(self):
|
|
|
525 return u16(0xbf10)
|
|
|
526
|
|
206
|
527 armtarget.check()
|
|
|
528
|
