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annotate cos/kernel/asmcode.asm @ 240:6259856841a0
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author | Windel Bouwman |
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date | Mon, 22 Jul 2013 22:37:33 +0200 |
parents | 91f91ff07ea8 |
children |
rev | line source |
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14 | 1 ; The default interrupt handlers. |
2 ; from 20 - 31 are reserved vectors. | |
3 ; below are the custom ones! | |
4 | |
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5 ; Calling convention AMD64 ABI: |
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6 ; parameters in: rdi, rsi, rdx, rcx .... |
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7 |
14 | 8 section .text |
9 align 4 | |
10 | |
25 | 11 ; Function to read the current instruction pointer value: |
12 global read_rip | |
13 read_rip: | |
14 pop rax | |
15 jmp rax | |
16 | |
14 | 17 global loadIDT |
18 loadIDT: | |
17 | 19 extern idtP |
20 ; TODO: make this pointer thing more insightfull: | |
21 lidt [idtP] | |
14 | 22 ret |
23 | |
32
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24 global setCR3 |
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25 setCR3: |
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26 mov cr3, rdi ; Load cr3 |
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27 ret |
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28 |
31 | 29 ; ISR related assembler wrappers: |
30 | |
31 %macro ISR_NOERRCODE 1 | |
32 global INT%1 | |
33 INT%1: | |
34 cli | |
35 push strict qword 0 ; push dummy error code | |
36 push strict qword %1 ; push interrupt number | |
37 jmp isr_common_stub | |
38 %endmacro | |
39 | |
40 %macro ISR_ERRCODE 1 | |
41 global INT%1 | |
42 INT%1: | |
36 | 43 cli ; disable interrupts |
31 | 44 push strict qword %1 ; push interrupt number |
45 jmp isr_common_stub | |
46 %endmacro | |
47 | |
48 isr_common_stub: | |
49 ; Do some saving: | |
36 | 50 push rax ; regs[6] |
17 | 51 push rcx |
52 push rdx | |
53 push rbx | |
54 push rbp | |
55 push rsi | |
36 | 56 push rdi ; regs[0] |
31 | 57 |
58 ; AMD64 calling convention, first parameter is in rdi: | |
59 mov rdi, rsp ; Load stack pointer into rdi to indicate where the registers on the stack are (so that we can change them!) | |
17 | 60 |
36 | 61 ; TODO: load kernel interrupt stack pointer |
31 | 62 extern isr_handler |
63 call isr_handler | |
64 | |
17 | 65 pop rdi |
66 pop rsi | |
67 pop rbp | |
68 pop rbx | |
69 pop rdx | |
70 pop rcx | |
71 pop rax | |
72 | |
31 | 73 add rsp, 16 ; cleanup error code and isr number |
36 | 74 sti ; enable interrupts again |
31 | 75 iretq |
14 | 76 |
77 ; Exception handlers: | |
31 | 78 ISR_NOERRCODE 0 |
79 ISR_NOERRCODE 1 | |
80 ISR_NOERRCODE 2 | |
81 ISR_NOERRCODE 3 | |
82 ISR_NOERRCODE 4 | |
83 ISR_NOERRCODE 5 | |
84 ISR_NOERRCODE 6 | |
85 ISR_NOERRCODE 7 | |
86 ISR_ERRCODE 8 | |
87 ISR_NOERRCODE 9 | |
88 ISR_ERRCODE 10 | |
89 ISR_ERRCODE 11 | |
90 ISR_ERRCODE 12 | |
91 ISR_ERRCODE 13 | |
92 ISR_ERRCODE 14 | |
93 ; 15 is reserved | |
94 ISR_NOERRCODE 16 | |
95 ISR_ERRCODE 17 | |
96 ISR_NOERRCODE 18 | |
97 ISR_NOERRCODE 19 | |
36 | 98 ; 20 - 31 are reserved |
14 | 99 |
33 | 100 ; irq handlers: |
31 | 101 ISR_NOERRCODE 32 |
102 ISR_NOERRCODE 33 | |
103 ISR_NOERRCODE 34 | |
33 | 104 ISR_NOERRCODE 35 |
105 ISR_NOERRCODE 36 | |
106 ISR_NOERRCODE 37 | |
107 ISR_NOERRCODE 38 | |
108 ISR_NOERRCODE 39 | |
109 ISR_NOERRCODE 40 | |
110 ISR_NOERRCODE 41 | |
111 ISR_NOERRCODE 42 | |
112 ISR_NOERRCODE 43 | |
113 ISR_NOERRCODE 44 | |
114 ISR_NOERRCODE 45 | |
115 ISR_NOERRCODE 46 | |
116 ISR_NOERRCODE 47 | |
14 | 117 |
31 | 118 ; default handler: |
119 ISR_NOERRCODE 255 | |
120 | |
121 |