annotate python/registerallocator.py @ 269:5f8c04a8d26b

Towards better modularity
author Windel Bouwman
date Sun, 18 Aug 2013 17:43:18 +0200
parents a51b3c956386
children cdc76d183bcc
rev   line source
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2 import graph
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4 class InterferenceGraphNode(graph.Node):
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5 def __init__(self, g, varname):
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6 super().__init__(g)
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7 self.varname = varname
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9 def __repr__(self):
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10 return '{}'.format(self.varname)
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13 class InterferenceGraph(graph.Graph):
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14 def __init__(self, flowgraph):
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15 """ Create a new interference graph from a flowgraph """
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16 super().__init__()
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17 # Mapping from node to live set
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18 self.liveMap = {}
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19 self.tempMap = {}
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20 # Calculate liveness in CFG:
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21 ###
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22 # Liveness:
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23 # in[n] = use[n] UNION (out[n] - def[n])
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24 # out[n] = for s in n.succ in union in[s]
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25 ###
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26 for n in flowgraph.nodes:
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27 n.live_in = set()
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28 n.live_out = set()
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29 # Dataflow fixed point iteration:
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30 change = True
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31 while change:
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32 change = False
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33 for n in flowgraph.nodes:
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34 _in = n.live_in
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35 _out = n.live_out
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36 n.live_in = n.uses | (n.live_out - n.defs)
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37 if n.succ:
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38 n.live_out = set.union(*(s.live_in for s in n.succ))
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39 else:
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40 n.live_out = set()
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41 change = change or (_in != n.live_in) or (_out != n.live_out)
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42 # Construct interference graph:
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43 for n in flowgraph.nodes:
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44 for tmp in n.live_out:
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45 n1 = self.getNode(tmp)
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46 for tmp2 in (n.live_out - {tmp}):
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47 n2 = self.getNode(tmp2)
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48 self.addEdge(n1, n2)
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49
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50 def getNode(self, tmp):
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51 if tmp not in self.tempMap:
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52 self.tempMap[tmp] = self.newNode(tmp)
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53 return self.tempMap[tmp]
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54
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55 def newNode(self, varname):
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56 n = InterferenceGraphNode(self, varname)
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57 self.nodes.append(n)
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58 return n
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61 class RegisterAllocator:
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62 """ Target independent register allocator """
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63 def registerAllocate(self, ig, regs):
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64 """ Color the given interference graph with the provided registers """
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65 self.regMap = {}
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66 # TODO: implement ;)
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67 regs = set(regs)
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68 for n in ig.nodes:
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69 print(n)
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71 # TODO: implement spilling
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72 # TODO: implement coalescing
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