|
292
|
1 import struct
|
|
334
|
2 from ppci.asmnodes import ASymbol, AInstruction, ANumber, AUnop, ABinop
|
|
292
|
3 from .basetarget import Register, Instruction, Target, Label, LabelRef
|
|
|
4 from .basetarget import Imm32, Imm8, Imm7, Imm3
|
|
|
5
|
|
|
6
|
|
|
7 def u16(h):
|
|
|
8 return struct.pack('<H', h)
|
|
|
9
|
|
|
10 def u32(x):
|
|
|
11 return struct.pack('<I', x)
|
|
|
12
|
|
|
13 # Operands:
|
|
|
14
|
|
|
15 class ArmRegister(Register):
|
|
|
16 def __init__(self, num, name):
|
|
|
17 super().__init__(name)
|
|
|
18 self.num = num
|
|
|
19
|
|
|
20 def __repr__(self):
|
|
|
21 return self.name
|
|
|
22
|
|
|
23 @classmethod
|
|
|
24 def Create(cls, vop):
|
|
|
25 if type(vop) is ASymbol:
|
|
|
26 name = vop.name
|
|
|
27 regs = {}
|
|
|
28 for r in registers:
|
|
|
29 regs[r.name] = r
|
|
|
30 if name in regs:
|
|
|
31 r = regs[name]
|
|
|
32 if isinstance(r, cls):
|
|
|
33 return r
|
|
|
34
|
|
|
35
|
|
|
36 class Reg8Op(ArmRegister):
|
|
|
37 pass
|
|
|
38
|
|
|
39
|
|
|
40 class Reg16Op(ArmRegister):
|
|
|
41 pass
|
|
|
42
|
|
|
43
|
|
|
44 R0 = Reg8Op(0, 'r0')
|
|
|
45 R1 = Reg8Op(1, 'r1')
|
|
|
46 R2 = Reg8Op(2, 'r2')
|
|
|
47 R3 = Reg8Op(3, 'r3')
|
|
|
48 R4 = Reg8Op(4, 'r4')
|
|
|
49 R5 = Reg8Op(5, 'r5')
|
|
|
50 R6 = Reg8Op(6, 'r6')
|
|
|
51 R7 = Reg8Op(7, 'r7')
|
|
|
52 # Other registers:
|
|
|
53 # TODO
|
|
|
54 SP = ArmRegister(13, 'sp')
|
|
|
55 LR = ArmRegister(14, 'lr')
|
|
|
56 PC = ArmRegister(15, 'pc')
|
|
|
57
|
|
|
58 registers = [R0, R1, R2, R3, R4, R5, R6, R7, SP, LR, PC]
|
|
|
59
|
|
|
60
|
|
|
61 class RegSpOp:
|
|
|
62 @classmethod
|
|
|
63 def Create(cls, vop):
|
|
|
64 if type(vop) is ASymbol:
|
|
|
65 if vop.name.lower() == 'sp':
|
|
|
66 return cls()
|
|
|
67
|
|
|
68
|
|
|
69 def getRegNum(n):
|
|
|
70 for r in registers:
|
|
|
71 if r.num == n:
|
|
|
72 return r
|
|
|
73
|
|
|
74
|
|
|
75 def getRegisterRange(n1, n2):
|
|
|
76 regs = []
|
|
|
77 if n1.num < n2.num:
|
|
|
78 for n in range(n1.num, n2.num + 1):
|
|
|
79 r = getRegNum(n)
|
|
|
80 assert r
|
|
|
81 regs.append(r)
|
|
|
82 return regs
|
|
|
83
|
|
|
84
|
|
|
85 def isRegOffset(regname, x, y):
|
|
|
86 if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname:
|
|
|
87 return y.number
|
|
|
88 elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname:
|
|
|
89 return x.number
|
|
|
90
|
|
|
91
|
|
|
92 class MemRegXRel:
|
|
|
93 def __init__(self, offset):
|
|
|
94 assert offset % 4 == 0
|
|
|
95 self.offset = offset
|
|
|
96
|
|
|
97 def __repr__(self):
|
|
|
98 return '[{}, #{}]'.format(self.regname, self.offset)
|
|
|
99
|
|
|
100 @classmethod
|
|
|
101 def Create(cls, vop):
|
|
|
102 if type(vop) is AUnop and vop.operation == '[]' and type(vop.arg) is ABinop and vop.arg.op == '+':
|
|
|
103 vop = vop.arg # descent
|
|
|
104 offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
|
|
|
105 if type(offset) is int:
|
|
|
106 if offset % 4 == 0:
|
|
|
107 offset = vop.arg2.number
|
|
|
108 return cls(offset)
|
|
|
109 elif type(vop) is ASymbol and vop.name.upper() == self.regname:
|
|
|
110 return cls(0)
|
|
|
111
|
|
|
112
|
|
|
113 class MemSpRel(MemRegXRel):
|
|
|
114 regname = 'SP'
|
|
|
115
|
|
|
116
|
|
|
117 class MemR8Rel:
|
|
|
118 def __init__(self, basereg, offset):
|
|
|
119 assert type(basereg) is Reg8Op
|
|
|
120 assert type(offset) is int
|
|
|
121 self.basereg = basereg
|
|
|
122 self.offset = offset
|
|
|
123
|
|
|
124 def __repr__(self):
|
|
|
125 return '[{}, #{}]'.format(self.basereg, self.offset)
|
|
|
126
|
|
|
127 @classmethod
|
|
|
128 def Create(cls, vop):
|
|
|
129 if type(vop) is AUnop and vop.operation == '[]':
|
|
|
130 vop = vop.arg # descent
|
|
|
131 if type(vop) is ABinop:
|
|
|
132 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
|
|
|
133 offset = vop.arg2.number
|
|
|
134 if offset > 120:
|
|
|
135 return
|
|
|
136 basereg = Reg8Op.Create(vop.arg1)
|
|
|
137 if not basereg:
|
|
|
138 return
|
|
|
139 else:
|
|
|
140 return
|
|
|
141 elif type(vop) is ASymbol:
|
|
|
142 offset = 0
|
|
|
143 basereg = Reg8Op.Create(vop)
|
|
|
144 if not basereg:
|
|
|
145 return
|
|
|
146 else:
|
|
|
147 return
|
|
|
148 return cls(getRegNum(basereg.num), offset)
|
|
|
149
|
|
|
150
|
|
|
151 class RegisterSet:
|
|
|
152 def __init__(self, regs):
|
|
|
153 assert type(regs) is set
|
|
|
154 self.regs = regs
|
|
|
155
|
|
|
156 def __repr__(self):
|
|
|
157 return ','.join([str(r) for r in self.regs])
|
|
|
158
|
|
|
159 @classmethod
|
|
|
160 def Create(cls, vop):
|
|
|
161 assert type(vop) is AUnop and vop.operation == '{}'
|
|
|
162 assert type(vop.arg) is list
|
|
|
163 regs = set()
|
|
|
164 for arg in vop.arg:
|
|
|
165 if type(arg) is ASymbol:
|
|
|
166 reg = ArmRegister.Create(arg)
|
|
|
167 if not reg:
|
|
|
168 return
|
|
|
169 regs.add(reg)
|
|
|
170 elif type(arg) is ABinop and arg.op == '-':
|
|
|
171 reg1 = ArmRegister.Create(arg.arg1)
|
|
|
172 reg2 = ArmRegister.Create(arg.arg2)
|
|
|
173 if not reg1:
|
|
|
174 return
|
|
|
175 if not reg2:
|
|
|
176 return
|
|
|
177 for r in getRegisterRange(reg1, reg2):
|
|
|
178 regs.add(r)
|
|
|
179 else:
|
|
|
180 raise Exception('Cannot be')
|
|
|
181 return cls(regs)
|
|
|
182
|
|
|
183 def registerNumbers(self):
|
|
|
184 return [r.num for r in self.regs]
|
|
|
185
|
|
|
186
|
|
|
187
|
|
|
188 # Instructions:
|
|
|
189
|
|
|
190 class ArmInstruction(Instruction):
|
|
|
191 pass
|
|
|
192
|
|
|
193
|
|
|
194 allins = []
|
|
|
195
|
|
|
196
|
|
|
197 def instruction(i):
|
|
|
198 allins.append(i)
|
|
|
199 return i
|
|
|
200
|
|
|
201
|
|
|
202 @instruction
|
|
|
203 class Dcd(ArmInstruction):
|
|
|
204 mnemonic = 'dcd'
|
|
|
205 operands = (Imm32,)
|
|
|
206 def __init__(self, expr):
|
|
|
207 if isinstance(expr, Imm32):
|
|
|
208 self.expr = expr.imm
|
|
|
209 self.label = None
|
|
|
210 elif isinstance(expr, LabelRef):
|
|
|
211 self.expr = 0
|
|
|
212 self.label = expr
|
|
|
213 elif isinstance(expr, int):
|
|
|
214 self.expr = expr
|
|
|
215 self.label = None
|
|
|
216 else:
|
|
|
217 raise NotImplementedError()
|
|
|
218
|
|
|
219 def encode(self):
|
|
|
220 return u32(self.expr)
|
|
|
221
|
|
335
|
222 def relocations(self):
|
|
|
223 assert not isinstance(self.expr, LabelRef)
|
|
|
224 return []
|
|
|
225
|
|
292
|
226 def __repr__(self):
|
|
|
227 return 'DCD 0x{0:X}'.format(self.expr)
|
|
|
228
|
|
|
229
|
|
|
230 @instruction
|
|
|
231 class nop_ins(ArmInstruction):
|
|
|
232 mnemonic = 'nop'
|
|
|
233 operands = tuple()
|
|
|
234
|
|
|
235 def encode(self):
|
|
|
236 return bytes()
|
|
|
237
|
|
|
238 def __repr__(self):
|
|
|
239 return 'NOP'
|
|
|
240
|
|
|
241
|
|
|
242 # Memory related
|
|
|
243
|
|
|
244 class LS_imm5_base(ArmInstruction):
|
|
|
245 """ ??? Rt, [Rn, imm5] """
|
|
|
246 operands = (Reg8Op, MemR8Rel)
|
|
|
247 def __init__(self, rt, memop):
|
|
|
248 assert memop.offset % 4 == 0
|
|
|
249 self.imm5 = memop.offset >> 2
|
|
|
250 self.rn = memop.basereg.num
|
|
|
251 self.rt = rt
|
|
|
252 self.memloc = memop
|
|
|
253 assert self.rn < 8
|
|
|
254 assert self.rt.num < 8
|
|
|
255
|
|
|
256 def encode(self):
|
|
|
257 Rn = self.rn
|
|
|
258 Rt = self.rt.num
|
|
|
259 imm5 = self.imm5
|
|
|
260
|
|
|
261 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
|
|
|
262 return u16(h)
|
|
|
263
|
|
|
264
|
|
|
265 def __repr__(self):
|
|
|
266 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
|
|
|
267
|
|
|
268
|
|
|
269 @instruction
|
|
|
270 class Str2(LS_imm5_base):
|
|
|
271 mnemonic = 'STR'
|
|
|
272 opcode = 0xC
|
|
|
273
|
|
|
274 @classmethod
|
|
|
275 def fromim(cls, im):
|
|
|
276 mem = MemR8Rel(im.src[0], im.others[0])
|
|
|
277 return cls(im.src[1], mem)
|
|
|
278
|
|
|
279
|
|
|
280 @instruction
|
|
|
281 class Ldr2(LS_imm5_base):
|
|
|
282 mnemonic = 'LDR'
|
|
|
283 opcode = 0xD
|
|
|
284
|
|
|
285 @classmethod
|
|
|
286 def fromim(cls, im):
|
|
|
287 mem = MemR8Rel(im.src[0], im.others[0])
|
|
|
288 return cls(im.dst[0], mem)
|
|
|
289
|
|
|
290 class ls_sp_base_imm8(ArmInstruction):
|
|
|
291 operands = (Reg8Op, MemSpRel)
|
|
|
292 def __init__(self, rt, memop):
|
|
|
293 self.rt = rt
|
|
|
294 self.offset = memop.offset
|
|
|
295
|
|
|
296 def encode(self):
|
|
|
297 rt = self.rt.num
|
|
|
298 assert rt < 8
|
|
|
299 imm8 = self.offset >> 2
|
|
|
300 assert imm8 < 256
|
|
|
301 h = (self.opcode << 8) | (rt << 8) | imm8
|
|
|
302 return u16(h)
|
|
|
303
|
|
|
304 def __repr__(self):
|
|
|
305 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset)
|
|
|
306
|
|
|
307 def align(x, m):
|
|
|
308 while ((x % m) != 0):
|
|
|
309 x = x + 1
|
|
|
310 return x
|
|
|
311
|
|
|
312
|
|
|
313 @instruction
|
|
|
314 class Ldr3(ArmInstruction):
|
|
|
315 """ ldr Rt, LABEL, load value from pc relative position """
|
|
|
316 mnemonic = 'ldr'
|
|
|
317 operands = (Reg8Op, LabelRef)
|
|
|
318 def __init__(self, rt, label):
|
|
|
319 assert isinstance(label, LabelRef)
|
|
|
320 self.rt = rt
|
|
|
321 self.label = label
|
|
|
322 self.offset = 0
|
|
|
323
|
|
|
324 @classmethod
|
|
|
325 def fromim(cls, im):
|
|
|
326 return cls(im.dst[0], im.others[0])
|
|
|
327
|
|
335
|
328 def relocations(self):
|
|
|
329 return [(self.label.name, 'lit_add_8')]
|
|
292
|
330
|
|
|
331 def encode(self):
|
|
|
332 rt = self.rt.num
|
|
|
333 assert rt < 8
|
|
|
334 assert self.offset % 4 == 0
|
|
|
335 imm8 = self.offset >> 2
|
|
|
336 assert imm8 < 256
|
|
|
337 assert imm8 >= 0
|
|
|
338 h = (0x9 << 11) | (rt << 8) | imm8
|
|
|
339 return u16(h)
|
|
|
340
|
|
|
341 def __repr__(self):
|
|
|
342 return 'LDR {}, {}'.format(self.rt, self.label.name)
|
|
|
343
|
|
|
344
|
|
|
345 @instruction
|
|
|
346 class Ldr1(ls_sp_base_imm8):
|
|
|
347 """ ldr Rt, [SP, imm8] """
|
|
|
348 mnemonic = 'LDR'
|
|
|
349 opcode = 0x98
|
|
|
350
|
|
|
351
|
|
|
352 @instruction
|
|
|
353 class Str1(ls_sp_base_imm8):
|
|
|
354 """ str Rt, [SP, imm8] """
|
|
|
355 mnemonic = 'STR'
|
|
|
356 opcode = 0x90
|
|
|
357
|
|
|
358
|
|
|
359 @instruction
|
|
|
360 class Mov3(ArmInstruction):
|
|
|
361 """ mov Rd, imm8, move immediate value into register """
|
|
|
362 mnemonic = 'mov'
|
|
|
363 opcode = 4 # 00100 Rd(3) imm8
|
|
|
364 operands = (Reg8Op, Imm8)
|
|
|
365 def __init__(self, rd, imm):
|
|
|
366 if type(imm) is int:
|
|
|
367 imm = Imm8(imm)
|
|
|
368 assert type(imm) is Imm8
|
|
|
369 self.imm = imm.imm
|
|
|
370 assert type(rd) is Reg8Op, str(type(rd))
|
|
|
371 self.rd = rd
|
|
|
372
|
|
|
373 @classmethod
|
|
|
374 def fromim(cls, im):
|
|
|
375 return cls(im.dst[0], im.others[0])
|
|
|
376
|
|
|
377 def encode(self):
|
|
|
378 rd = self.rd.num
|
|
|
379 opcode = self.opcode
|
|
|
380 imm8 = self.imm
|
|
|
381 h = (opcode << 11) | (rd << 8) | imm8
|
|
|
382 return u16(h)
|
|
|
383
|
|
|
384 def __repr__(self):
|
|
|
385 return 'MOV {}, {}'.format(self.rd, self.imm)
|
|
|
386
|
|
|
387
|
|
|
388
|
|
|
389 # Arithmatics:
|
|
|
390
|
|
|
391
|
|
|
392
|
|
|
393 class regregimm3_base(ArmInstruction):
|
|
|
394 operands = (Reg8Op, Reg8Op, Imm3)
|
|
|
395 def __init__(self, rd, rn, imm3):
|
|
|
396 self.rd = rd
|
|
|
397 self.rn = rn
|
|
|
398 assert type(imm3) is Imm3
|
|
|
399 self.imm3 = imm3
|
|
|
400
|
|
|
401 @classmethod
|
|
|
402 def fromim(cls, im):
|
|
|
403 return cls(im.dst[0], im.src[0], im.others[0])
|
|
|
404
|
|
|
405 def encode(self):
|
|
|
406 rd = self.rd.num
|
|
|
407 rn = self.rn.num
|
|
|
408 imm3 = self.imm3.imm
|
|
|
409 opcode = self.opcode
|
|
|
410 h = (self.opcode << 9) | (imm3 << 6) | (rn << 3) | rd
|
|
|
411 return u16(h)
|
|
|
412
|
|
|
413 def __repr__(self):
|
|
|
414 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.imm3.imm)
|
|
|
415
|
|
|
416 @instruction
|
|
300
|
417 class Add2(regregimm3_base):
|
|
292
|
418 """ add Rd, Rn, imm3 """
|
|
|
419 mnemonic = 'add'
|
|
|
420 opcode = 0b0001110
|
|
|
421
|
|
|
422
|
|
|
423 @instruction
|
|
300
|
424 class Sub2(regregimm3_base):
|
|
292
|
425 """ sub Rd, Rn, imm3 """
|
|
|
426 mnemonic = 'sub'
|
|
|
427 opcode = 0b0001111
|
|
|
428
|
|
|
429
|
|
|
430 class regregreg_base(ArmInstruction):
|
|
|
431 """ ??? Rd, Rn, Rm """
|
|
|
432 operands = (Reg8Op, Reg8Op, Reg8Op)
|
|
|
433 def __init__(self, rd, rn, rm):
|
|
|
434 self.rd = rd
|
|
|
435 self.rn = rn
|
|
|
436 self.rm = rm
|
|
|
437
|
|
|
438 @classmethod
|
|
|
439 def fromim(cls, im):
|
|
|
440 return cls(im.dst[0], im.src[0], im.src[1])
|
|
|
441
|
|
|
442 def encode(self):
|
|
|
443 rd = self.rd.num
|
|
|
444 rn = self.rn.num
|
|
|
445 rm = self.rm.num
|
|
|
446 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd
|
|
|
447 return u16(h)
|
|
|
448
|
|
|
449 def __repr__(self):
|
|
|
450 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
|
|
|
451
|
|
|
452
|
|
|
453 @instruction
|
|
|
454 class Add(regregreg_base):
|
|
|
455 mnemonic = 'ADD'
|
|
|
456 opcode = 0b0001100
|
|
|
457
|
|
|
458
|
|
|
459 @instruction
|
|
|
460 class Sub(regregreg_base):
|
|
|
461 mnemonic = 'SUB'
|
|
|
462 opcode = 0b0001101
|
|
|
463
|
|
|
464
|
|
|
465 @instruction
|
|
|
466 class Mov2(ArmInstruction):
|
|
|
467 """ mov rd, rm """
|
|
|
468 operands = (ArmRegister, ArmRegister)
|
|
|
469 mnemonic = 'MOV'
|
|
|
470 def __init__(self, rd, rm):
|
|
|
471 self.rd = rd
|
|
|
472 self.rm = rm
|
|
|
473
|
|
|
474 @classmethod
|
|
|
475 def fromim(cls, im):
|
|
|
476 return cls(im.dst[0], im.src[0])
|
|
|
477
|
|
|
478 def encode(self):
|
|
|
479 Rd = self.rd.num & 0x7
|
|
|
480 D = (self.rd.num >> 3) & 0x1
|
|
|
481 Rm = self.rm.num
|
|
|
482 opcode = 0b01000110
|
|
|
483 return u16((opcode << 8) | (D << 7) |(Rm << 3) | Rd)
|
|
|
484
|
|
|
485 def __repr__(self):
|
|
|
486 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm)
|
|
335
|
487
|
|
292
|
488
|
|
|
489 @instruction
|
|
300
|
490 class Mul(ArmInstruction):
|
|
292
|
491 """ mul Rn, Rdm """
|
|
|
492 operands = (Reg8Op, Reg8Op)
|
|
|
493 mnemonic = 'MUL'
|
|
|
494 def __init__(self, rn, rdm):
|
|
|
495 self.rn = rn
|
|
|
496 self.rdm = rdm
|
|
|
497
|
|
|
498 @classmethod
|
|
|
499 def fromim(cls, im):
|
|
|
500 assert im.src[1] is im.dst[0]
|
|
|
501 return cls(im.src[0], im.dst[0])
|
|
|
502
|
|
|
503 def encode(self):
|
|
|
504 rn = self.rn.num
|
|
|
505 rdm = self.rdm.num
|
|
|
506 opcode = 0b0100001101
|
|
|
507 h = (opcode << 6) | (rn << 3) | rdm
|
|
|
508 return u16(h)
|
|
|
509
|
|
|
510 def __repr__(self):
|
|
|
511 return '{} {}, {}'.format(self.mnemonic, self.rn, self.rdm)
|
|
|
512
|
|
|
513
|
|
|
514 class regreg_base(ArmInstruction):
|
|
|
515 """ ??? Rdn, Rm """
|
|
|
516 operands = (Reg8Op, Reg8Op)
|
|
|
517 # TODO: integrate with the code gen interface:
|
|
|
518 src = (0, 1)
|
|
|
519 dst = (0,)
|
|
|
520 def __init__(self, rdn, rm):
|
|
|
521 self.rdn = rdn
|
|
|
522 self.rm = rm
|
|
|
523
|
|
|
524 @classmethod
|
|
|
525 def fromim(cls, im):
|
|
|
526 return cls(im.src[0], im.src[1])
|
|
|
527
|
|
|
528 def encode(self):
|
|
|
529 rdn = self.rdn.num
|
|
|
530 rm = self.rm.num
|
|
|
531 h = (self.opcode << 6) | (rm << 3) | rdn
|
|
|
532 return u16(h)
|
|
|
533
|
|
|
534 def __repr__(self):
|
|
|
535 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
|
|
|
536
|
|
|
537
|
|
|
538 @instruction
|
|
|
539 class movregreg_ins(regreg_base):
|
|
|
540 """ mov Rd, Rm (reg8 operands) """
|
|
|
541 mnemonic = 'mov'
|
|
|
542 opcode = 0
|
|
|
543
|
|
|
544
|
|
|
545 @instruction
|
|
|
546 class And(regreg_base):
|
|
|
547 mnemonic = 'AND'
|
|
|
548 opcode = 0b0100000000
|
|
|
549
|
|
|
550
|
|
|
551 @instruction
|
|
|
552 class Orr(regreg_base):
|
|
|
553 mnemonic = 'ORR'
|
|
|
554 opcode = 0b0100001100
|
|
|
555
|
|
|
556
|
|
|
557 @instruction
|
|
|
558 class Cmp(regreg_base):
|
|
|
559 mnemonic = 'CMP'
|
|
|
560 opcode = 0b0100001010
|
|
|
561
|
|
|
562
|
|
|
563 @instruction
|
|
|
564 class Lsl(regreg_base):
|
|
|
565 mnemonic = 'LSL'
|
|
|
566 opcode = 0b0100000010
|
|
|
567
|
|
|
568
|
|
|
569 @instruction
|
|
|
570 class cmpregimm8_ins(ArmInstruction):
|
|
|
571 """ cmp Rn, imm8 """
|
|
|
572 mnemonic = 'cmp'
|
|
|
573 opcode = 5 # 00101
|
|
|
574 operands = (Reg8Op, Imm8)
|
|
|
575 def __init__(self, rn, imm):
|
|
|
576 self.rn = rn
|
|
|
577 self.imm = imm
|
|
|
578
|
|
|
579 def encode(self):
|
|
|
580 rn = self.rn.num
|
|
|
581 imm = self.imm.imm
|
|
|
582 opcode = self.opcode
|
|
|
583 h = (opcode << 11) | (rn << 8) | imm
|
|
|
584 return u16(h)
|
|
|
585
|
|
|
586
|
|
|
587 # Jumping:
|
|
|
588
|
|
|
589 def wrap_negative(x, bits):
|
|
|
590 b = struct.unpack('<I', struct.pack('<i', x))[0]
|
|
|
591 mask = (1 << bits) - 1
|
|
|
592 return b & mask
|
|
|
593
|
|
|
594 class jumpBase_ins(ArmInstruction):
|
|
|
595 operands = (LabelRef,)
|
|
|
596 def __init__(self, target_label):
|
|
|
597 assert type(target_label) is LabelRef
|
|
|
598 self.target = target_label
|
|
|
599 self.offset = 0
|
|
|
600
|
|
|
601 def __repr__(self):
|
|
|
602 return '{} {}'.format(self.mnemonic, self.target.name)
|
|
|
603
|
|
|
604
|
|
335
|
605 class Imm11Reloc:
|
|
|
606 def apply(self, P, S):
|
|
|
607 pass
|
|
|
608
|
|
|
609
|
|
292
|
610 @instruction
|
|
|
611 class B(jumpBase_ins):
|
|
|
612 mnemonic = 'B'
|
|
|
613 def encode(self):
|
|
|
614 imm11 = wrap_negative(self.offset >> 1, 11)
|
|
|
615 h = (0b11100 << 11) | imm11 # | 1 # 1 to enable thumb mode
|
|
|
616 return u16(h)
|
|
|
617
|
|
335
|
618 def relocations(self):
|
|
|
619 return [(self.target.name, 'wrap_new11')]
|
|
292
|
620
|
|
|
621 @instruction
|
|
|
622 class Bl(jumpBase_ins):
|
|
|
623 mnemonic = 'BL'
|
|
|
624 def encode(self):
|
|
|
625 imm32 = wrap_negative(self.offset >> 1, 32)
|
|
|
626 imm11 = imm32 & 0x7FF
|
|
|
627 imm10 = (imm32 >> 11) & 0x3FF
|
|
|
628 j1 = 1 # TODO: what do these mean?
|
|
|
629 j2 = 1
|
|
|
630 s = (imm32 >> 24) & 0x1
|
|
|
631 h1 = (0b11110 << 11) | (s << 10) | imm10
|
|
|
632 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11
|
|
|
633 return u16(h1) + u16(h2)
|
|
|
634
|
|
335
|
635 def relocations(self):
|
|
|
636 return [(self.target.name, 'bl_imm11_imm10')]
|
|
292
|
637
|
|
335
|
638
|
|
|
639 class cond_base_ins_short(jumpBase_ins):
|
|
292
|
640 def encode(self):
|
|
|
641 imm8 = wrap_negative(self.offset >> 1, 8)
|
|
|
642 h = (0b1101 << 12) | (self.cond << 8) | imm8
|
|
|
643 return u16(h)
|
|
|
644
|
|
335
|
645 def relocations(self):
|
|
|
646 return [(self.target.name, 'rel8')]
|
|
|
647
|
|
|
648
|
|
|
649 class cond_base_ins(jumpBase_ins):
|
|
|
650 """ Encoding T3 """
|
|
|
651 def encode(self):
|
|
|
652 j1 = 1 # TODO: what do these mean?
|
|
|
653 j2 = 1
|
|
|
654 h1 = (0b11110 << 11) | (self.cond << 6)
|
|
|
655 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11)
|
|
|
656 return u16(h1) + u16(h2)
|
|
|
657
|
|
|
658 def relocations(self):
|
|
|
659 return [(self.target.name, 'b_imm11_imm6')]
|
|
|
660
|
|
292
|
661
|
|
|
662 @instruction
|
|
|
663 class Beq(cond_base_ins):
|
|
|
664 mnemonic = 'beq'
|
|
|
665 cond = 0
|
|
|
666
|
|
|
667
|
|
|
668 @instruction
|
|
|
669 class Bne(cond_base_ins):
|
|
|
670 mnemonic = 'bne'
|
|
|
671 cond = 1
|
|
|
672
|
|
|
673
|
|
|
674 @instruction
|
|
|
675 class Blt(cond_base_ins):
|
|
|
676 mnemonic = 'blt'
|
|
|
677 cond = 0b1011
|
|
|
678
|
|
|
679
|
|
|
680 @instruction
|
|
|
681 class Bgt(cond_base_ins):
|
|
|
682 mnemonic = 'bgt'
|
|
|
683 cond = 0b1100
|
|
|
684
|
|
|
685
|
|
|
686 @instruction
|
|
|
687 class Push(ArmInstruction):
|
|
|
688 operands = (RegisterSet,)
|
|
|
689 mnemonic = 'push'
|
|
|
690
|
|
|
691 def __init__(self, regs):
|
|
|
692 if type(regs) is set:
|
|
|
693 regs = RegisterSet(regs)
|
|
|
694 assert (type(regs),) == self.operands, (type(regs),)
|
|
|
695 self.regs = regs
|
|
|
696
|
|
|
697 def __repr__(self):
|
|
|
698 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
|
|
|
699
|
|
|
700 def encode(self):
|
|
|
701 reg_list = 0
|
|
|
702 M = 0
|
|
|
703 for n in self.regs.registerNumbers():
|
|
|
704 if n < 8:
|
|
|
705 reg_list |= (1 << n)
|
|
|
706 elif n == 14:
|
|
|
707 M = 1
|
|
|
708 else:
|
|
|
709 raise NotImplementedError('not implemented for this register')
|
|
|
710 h = (0x5a << 9) | (M << 8) | reg_list
|
|
|
711 return u16(h)
|
|
|
712
|
|
|
713
|
|
|
714 @instruction
|
|
|
715 class Pop(ArmInstruction):
|
|
|
716 operands = (RegisterSet,)
|
|
|
717 mnemonic = 'pop'
|
|
|
718
|
|
|
719 def __init__(self, regs):
|
|
|
720 if type(regs) is set:
|
|
|
721 regs = RegisterSet(regs)
|
|
|
722 assert (type(regs),) == self.operands, (type(regs),)
|
|
|
723 self.regs = regs
|
|
|
724
|
|
|
725 def __repr__(self):
|
|
|
726 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
|
|
|
727
|
|
|
728 def encode(self):
|
|
|
729 reg_list = 0
|
|
|
730 P = 0
|
|
|
731 for n in self.regs.registerNumbers():
|
|
|
732 if n < 8:
|
|
|
733 reg_list |= (1 << n)
|
|
|
734 elif n == 15:
|
|
|
735 P = 1
|
|
|
736 else:
|
|
|
737 raise NotImplementedError('not implemented for this register')
|
|
|
738 h = (0x5E << 9) | (P << 8) | reg_list
|
|
|
739 return u16(h)
|
|
|
740
|
|
|
741
|
|
|
742 @instruction
|
|
|
743 class Yield(ArmInstruction):
|
|
|
744 operands = ()
|
|
|
745 mnemonic = 'yield'
|
|
|
746
|
|
|
747 def encode(self):
|
|
|
748 return u16(0xbf10)
|
|
|
749
|
|
|
750 # misc:
|
|
|
751
|
|
|
752 # add/sub SP:
|
|
|
753 class addspsp_base(ArmInstruction):
|
|
|
754 operands = (RegSpOp, RegSpOp, Imm7)
|
|
|
755 def __init__(self, _sp, _sp2, imm7):
|
|
|
756 self.imm7 = imm7.imm
|
|
|
757 assert self.imm7 % 4 == 0
|
|
|
758 self.imm7 >>= 2
|
|
|
759
|
|
|
760 def encode(self):
|
|
|
761 return u16((self.opcode << 7) |self.imm7)
|
|
|
762
|
|
|
763 def __repr__(self):
|
|
|
764 return '{} sp, sp, {}'.format(self.mnemonic, self.imm7 << 2)
|
|
|
765
|
|
305
|
766
|
|
292
|
767 @instruction
|
|
|
768 class AddSp(addspsp_base):
|
|
|
769 mnemonic = 'add'
|
|
|
770 opcode = 0b101100000
|
|
|
771
|
|
|
772
|
|
|
773 @instruction
|
|
|
774 class SubSp(addspsp_base):
|
|
|
775 mnemonic = 'sub'
|
|
|
776 opcode = 0b101100001
|
