annotate python/x86.py @ 244:58155c7c4a8e

Add hexutil
author Windel Bouwman
date Wed, 24 Jul 2013 19:47:13 +0200
parents 6b2bec5653f1
children
rev   line source
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1 import ppci
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2 import ir
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3
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4 class X86CodeGenSimple:
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5 """
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6 Inefficient code generation, assume stack machine
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7 backend
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8 """
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9 def __init__(self, diag):
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10 self.diag = diag
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11
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12 def emit(self, i):
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13 self.asm.append(i)
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14
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15 def genBin(self, ir):
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16 self.asm = []
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17 self.genModule(ir)
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18 return self.asm
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19
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20 def genModule(self, ir):
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21 for f in ir.Functions:
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22 self.genFunction(f)
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23 def genFunction(self, f):
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24 self.emit('global {0}'.format(f.name))
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25 self.emit('{0}:'.format(f.name))
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26 self.emit('jmp {0}'.format(f.entry.name))
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27 for bb in f.BasicBlocks:
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28 self.genBB(bb)
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29 def genBB(self, bb):
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30 self.emit('{0}:'.format(bb.name))
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31 for i in bb.Instructions:
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32 self.genIns(i)
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33 def genIns(self, i):
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34 if type(i) is ir.BinaryOperator:
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35 ops = {'+':'add', '-':'sub', '*':'mul'}
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36 if i.operation in ops:
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37 i.result.reg = 'rax'
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38 i.value1.reg = 'rbx'
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39 i.value2.reg = 'rbx'
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40 self.emit('mov {0}, {1}'.format(i.result.reg, i.value1.reg))
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41 self.emit('{0} {1}, {2}'.format(ops[i.operation], i.result.reg, i.value2.reg))
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42 else:
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43 raise NotImplementedError('op {0}'.format(i.operation))
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44 elif type(i) is ir.Load:
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45 self.emit('mov {0}, [{1}]'.format(i.value, i.location))
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46 elif type(i) is ir.Return:
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47 self.emit('ret')
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48 elif type(i) is ir.Call:
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49 self.emit('call')
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50 elif type(i) is ir.ImmLoad:
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51 self.emit('mov {0}, {1}'.format(i.target, i.value))
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52 elif type(i) is ir.Store:
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53 self.emit('mov [{0}], {1}'.format(i.location, i.value))
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54 elif type(i) is ir.ConditionalBranch:
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55 self.emit('cmp {0}, {1}'.format(i.a, i.b))
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56 jmps = {'>':'jg', '<':'jl', '==':'je'}
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57 if i.cond in jmps:
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58 j = jmps[i.cond]
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59 self.emit('{0} {1}'.format(j, i.lab1.name))
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60 else:
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61 raise NotImplementedError('condition {0}'.format(i.cond))
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62 self.emit('jmp {0}'.format(i.lab2.name))
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63 elif type(i) is ir.Branch:
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64 self.emit('jmp {0}'.format(i.target.name))
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65 elif type(i) is ir.Alloc:
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66 pass
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67 else:
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68 raise NotImplementedError('{0}'.format(i))
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69