annotate python/ppci/target/thumb/instructions.py @ 367:577ed7fb3fe4

Try to make thumb work again
author Windel Bouwman
date Fri, 21 Mar 2014 10:27:57 +0100
parents 3bb7dcfe5529
children
rev   line source
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1 from ..basetarget import Register, Instruction, Target, Label
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2 from ..token import u16, u32
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3 from .armtoken import ThumbToken
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4 from ..arm.registers import R0, ArmRegister, SP
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5
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6
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7 # Instructions:
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8
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9 class ThumbInstruction(Instruction):
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10 pass
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11
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12
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13 class Dcd(ThumbInstruction):
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14 def __init__(self, expr):
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15 if isinstance(expr, int):
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16 self.expr = expr
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17 self.label = None
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18 else:
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19 raise NotImplementedError()
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20
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21 def encode(self):
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22 return u32(self.expr)
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23
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24 def relocations(self):
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25 return []
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26
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27 def __repr__(self):
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28 return 'DCD 0x{0:X}'.format(self.expr)
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29
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30
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31 class nop_ins(ThumbInstruction):
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32 def encode(self):
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33 return bytes()
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34
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35 def __repr__(self):
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36 return 'NOP'
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37
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38
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39 # Memory related
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40
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41 class LS_imm5_base(ThumbInstruction):
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42 """ ??? Rt, [Rn, imm5] """
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43 def __init__(self, rt, rn, imm5):
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44 assert imm5 % 4 == 0
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45 self.imm5 = imm5 >> 2
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46 self.rn = rn
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47 self.rt = rt
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48 assert self.rn.num < 8
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49 assert self.rt.num < 8
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50 self.token = ThumbToken()
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51
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52 def encode(self):
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53 Rn = self.rn.num
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54 Rt = self.rt.num
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55 imm5 = self.imm5
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56 self.token[0:3] = Rt
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57 self.token[3:6] = Rn
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58 self.token[6:11] = imm5
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59 self.token[11:16] = self.opcode
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60 return self.token.encode()
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61
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62 def __repr__(self):
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63 mnemonic = "???"
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64 return '{} {}, [{}, {}]'.format(mnemonic, self.rt, self.rn, self.imm5)
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65
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66
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67 class Str2(LS_imm5_base):
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68 opcode = 0xC
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69
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70
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71 class Ldr2(LS_imm5_base):
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72 opcode = 0xD
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73
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74
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75 class ls_sp_base_imm8(ThumbInstruction):
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76 def __init__(self, rt, offset):
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77 self.rt = rt
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78 self.offset = offset
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79
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80 def encode(self):
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81 rt = self.rt.num
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82 assert rt < 8
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83 imm8 = self.offset >> 2
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84 assert imm8 < 256
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85 h = (self.opcode << 8) | (rt << 8) | imm8
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86 return u16(h)
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87
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88 def __repr__(self):
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89 mnemonic = self.__class__.__name__
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90 return '{} {}, [sp,#{}]'.format(mnemonic, self.rt, self.offset)
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91
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92
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93 def Ldr(*args):
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94 if len(args) == 2 and isinstance(args[0], ArmRegister) \
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95 and isinstance(args[1], str):
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96 return Ldr3(*args)
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97 else:
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98 raise Exception()
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99
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100
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101 class Ldr3(ThumbInstruction):
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102 """ ldr Rt, LABEL, load value from pc relative position """
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103 def __init__(self, rt, label):
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104 self.rt = rt
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105 self.label = label
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106
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107 def relocations(self):
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108 return [(self.label, 'lit_add_8')]
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109
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110 def encode(self):
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111 rt = self.rt.num
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112 assert rt < 8
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113 imm8 = 0
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114 h = (0x9 << 11) | (rt << 8) | imm8
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115 return u16(h)
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116
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117 def __repr__(self):
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118 return 'LDR {}, {}'.format(self.rt, self.label)
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119
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120
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121 class Ldr1(ls_sp_base_imm8):
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122 """ ldr Rt, [SP, imm8] """
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123 opcode = 0x98
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124
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125
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126 class Str1(ls_sp_base_imm8):
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127 """ str Rt, [SP, imm8] """
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128 opcode = 0x90
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129
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130
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131 class Mov3(ThumbInstruction):
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132 """ mov Rd, imm8, move immediate value into register """
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133 opcode = 4 # 00100 Rd(3) imm8
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134 def __init__(self, rd, imm):
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135 assert imm < 256
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136 self.imm = imm
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137 self.rd = rd
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138 self.token = ThumbToken()
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139
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140 def encode(self):
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141 rd = self.rd.num
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142 self.token[8:11] = rd
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143 self.token[0:8] = self.imm
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144 self.token[11:16] = self.opcode
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145 return self.token.encode()
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146
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147 def __repr__(self):
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148 return 'MOV {}, {}'.format(self.rd, self.imm)
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149
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150
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151 # Arithmatics:
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152
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153
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154 class regregimm3_base(ThumbInstruction):
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155 def __init__(self, rd, rn, imm3):
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156 self.rd = rd
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157 self.rn = rn
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158 assert imm3 < 8
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159 self.imm3 = imm3
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160 self.token = ThumbToken()
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161
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162 def encode(self):
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163 rd = self.rd.num
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164 self.token[0:3] = rd
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165 self.token[3:6] = self.rn.num
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166 self.token[6:9] = self.imm3
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167 self.token[9:16] = self.opcode
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168 return self.token.encode()
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169
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170 def __repr__(self):
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171 mnemonic = self.__class__.__name__
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172 return '{} {}, {}, {}'.format(mnemonic, self.rd, self.rn, self.imm3)
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173
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174
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175
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176 class Add2(regregimm3_base):
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177 """ add Rd, Rn, imm3 """
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178 opcode = 0b0001110
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179
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180
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181 class Sub2(regregimm3_base):
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182 """ sub Rd, Rn, imm3 """
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183 opcode = 0b0001111
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184
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185
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186 def Sub(*args):
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187 if len(args) == 3 and args[0] is SP and args[1] is SP and \
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188 isinstance(args[2], int) and args[2] < 256:
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189 return SubSp(args[2])
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190 elif len(args) == 3 and isinstance(args[0], ArmRegister) and \
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191 isinstance(args[1], ArmRegister) and isinstance(args[2], int) and \
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192 args[2] < 8:
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193 return Sub2(args[0], args[1], args[2])
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194 else:
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195 raise Exception()
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196
342
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197
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198 def Add(*args):
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199 if len(args) == 3 and args[0] is SP and args[1] is SP and \
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200 isinstance(args[2], int) and args[2] < 256:
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201 return AddSp(args[2])
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202 elif len(args) == 3 and isinstance(args[0], ArmRegister) and \
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203 isinstance(args[1], ArmRegister) and isinstance(args[2], int) and \
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204 args[2] < 8:
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205 return Add2(args[0], args[1], args[2])
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206 else:
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207 raise Exception()
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208
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209
341
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210 class regregreg_base(ThumbInstruction):
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211 """ ??? Rd, Rn, Rm """
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212 def __init__(self, rd, rn, rm):
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213 self.rd = rd
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214 self.rn = rn
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215 self.rm = rm
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216
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217 def encode(self):
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218 at = ThumbToken()
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219 at.rd = self.rd.num
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220 rn = self.rn.num
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221 rm = self.rm.num
336
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222 at[3:6] = rn
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223 at[6:9] = rm
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224 at[9:16] = self.opcode
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225 return at.encode()
292
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226
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227 def __repr__(self):
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228 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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229
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230
341
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231 class Add3(regregreg_base):
292
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232 mnemonic = 'ADD'
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233 opcode = 0b0001100
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234
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235
341
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236 class Sub3(regregreg_base):
292
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237 mnemonic = 'SUB'
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238 opcode = 0b0001101
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239
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240
341
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241 class Mov2(ThumbInstruction):
292
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242 """ mov rd, rm """
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243 mnemonic = 'MOV'
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244 def __init__(self, rd, rm):
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245 self.rd = rd
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246 self.rm = rm
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247
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248 def encode(self):
340
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249 at = ThumbToken()
336
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250 at.rd = self.rd.num & 0x7
292
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251 D = (self.rd.num >> 3) & 0x1
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252 Rm = self.rm.num
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253 opcode = 0b01000110
336
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254 at[8:16] = opcode
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255 at[3:7] = Rm
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256 at[7] = D
341
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257 return at.encode()
292
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258
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259 def __repr__(self):
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260 return '{} {}, {}'.format(self.mnemonic, self.rd, self.rm)
335
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diff changeset
261
292
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262
341
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diff changeset
263 class Mul(ThumbInstruction):
292
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264 """ mul Rn, Rdm """
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265 mnemonic = 'MUL'
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266 def __init__(self, rn, rdm):
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267 self.rn = rn
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268 self.rdm = rdm
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269
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270 def encode(self):
340
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271 at = ThumbToken()
292
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272 rn = self.rn.num
336
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diff changeset
273 at.rd = self.rdm.num
292
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274 opcode = 0b0100001101
336
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275 #h = (opcode << 6) | (rn << 3) | rdm
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276 at[6:16] = opcode
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277 at[3:6] = rn
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278 return at.encode()
292
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279
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280 def __repr__(self):
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281 return '{} {}, {}'.format(self.mnemonic, self.rn, self.rdm)
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282
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283
341
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diff changeset
284 class regreg_base(ThumbInstruction):
292
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285 """ ??? Rdn, Rm """
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286 def __init__(self, rdn, rm):
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287 self.rdn = rdn
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288 self.rm = rm
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289
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290 def encode(self):
340
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diff changeset
291 at = ThumbToken()
336
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diff changeset
292 at.rd = self.rdn.num
292
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293 rm = self.rm.num
336
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diff changeset
294 at[3:6] = rm
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diff changeset
295 at[6:16] = self.opcode
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diff changeset
296 return at.encode()
292
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297
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298 def __repr__(self):
341
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diff changeset
299 mnemonic = self.__class__.__name__
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diff changeset
300 return '{} {}, {}'.format(mnemonic, self.rdn, self.rm)
292
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301
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302
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303 class movregreg_ins(regreg_base):
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304 """ mov Rd, Rm (reg8 operands) """
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305 opcode = 0
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306
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307
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308 class And(regreg_base):
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309 opcode = 0b0100000000
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310
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311
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312 class Orr(regreg_base):
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313 opcode = 0b0100001100
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314
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315
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316 class Cmp(regreg_base):
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317 opcode = 0b0100001010
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318
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319
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320 class Lsl(regreg_base):
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321 opcode = 0b0100000010
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322
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diff changeset
323
342
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diff changeset
324 class Cmp2(ThumbInstruction):
292
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diff changeset
325 """ cmp Rn, imm8 """
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326 opcode = 5 # 00101
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327 def __init__(self, rn, imm):
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328 self.rn = rn
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329 self.imm = imm
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330
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331 def encode(self):
341
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diff changeset
332 at = ThumbToken()
342
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diff changeset
333 at[0:8] = self.imm
341
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diff changeset
334 at[8:11] = self.rn.num
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diff changeset
335 at[11:16] = self.opcode
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diff changeset
336 return at.encode()
292
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337
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338
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diff changeset
339 # Jumping:
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340
341
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diff changeset
341 class jumpBase_ins(ThumbInstruction):
292
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342 def __init__(self, target_label):
342
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diff changeset
343 assert type(target_label) is str
292
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344 self.target = target_label
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345 self.offset = 0
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346
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347 def __repr__(self):
341
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diff changeset
348 mnemonic = self.__class__.__name__
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diff changeset
349 return '{} {}'.format(mnemonic, self.target)
292
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350
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diff changeset
351
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352 class B(jumpBase_ins):
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353 def encode(self):
341
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diff changeset
354 h = (0b11100 << 11) | 0
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diff changeset
355 # | 1 # 1 to enable thumb mode
292
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356 return u16(h)
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357
335
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diff changeset
358 def relocations(self):
341
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diff changeset
359 return [(self.target, 'wrap_new11')]
292
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360
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361 class Bl(jumpBase_ins):
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362 def encode(self):
341
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diff changeset
363 imm11 = 0
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diff changeset
364 imm10 = 0
292
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diff changeset
365 j1 = 1 # TODO: what do these mean?
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diff changeset
366 j2 = 1
341
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diff changeset
367 s = 0
292
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parents:
diff changeset
368 h1 = (0b11110 << 11) | (s << 10) | imm10
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369 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11) | imm11
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370 return u16(h1) + u16(h2)
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371
335
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diff changeset
372 def relocations(self):
341
4d204f6f7d4e Rewrite of assembler parts
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diff changeset
373 return [(self.target, 'bl_imm11_imm10')]
292
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374
335
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diff changeset
375
336
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diff changeset
376 class cond_base_ins(jumpBase_ins):
292
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377 def encode(self):
341
4d204f6f7d4e Rewrite of assembler parts
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diff changeset
378 imm8 = 0
292
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379 h = (0b1101 << 12) | (self.cond << 8) | imm8
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380 return u16(h)
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381
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382 def relocations(self):
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383 return [(self.target, 'rel8')]
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384
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385
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386 class cond_base_ins_long(jumpBase_ins):
335
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387 """ Encoding T3 """
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388 def encode(self):
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389 j1 = 1 # TODO: what do these mean?
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390 j2 = 1
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391 h1 = (0b11110 << 11) | (self.cond << 6)
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392 h2 = (0b1101 << 12) | (j1 << 13) | (j2 << 11)
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393 return u16(h1) + u16(h2)
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394
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395 def relocations(self):
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396 return [(self.target, 'b_imm11_imm6')]
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397
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398
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399 class Beq(cond_base_ins):
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400 cond = 0
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401
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402
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403 class Bne(cond_base_ins):
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404 cond = 1
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405
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406
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407 class Blt(cond_base_ins):
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408 cond = 0b1011
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409
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410
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411 class Bgt(cond_base_ins):
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412 cond = 0b1100
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413
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414
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415 class Push(ThumbInstruction):
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416 def __init__(self, regs):
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417 assert type(regs) is set
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418 self.regs = regs
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419
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420 def __repr__(self):
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421 return 'Push {{{}}}'.format(self.regs)
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422
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423 def encode(self):
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424 at = ThumbToken()
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425 for n in register_numbers(self.regs):
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426 if n < 8:
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427 at[n] = 1
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428 elif n == 14:
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429 at[8] = 1
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430 else:
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431 raise NotImplementedError('not implemented for {}'.format(n))
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432 at[9:16] = 0x5a
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433 return at.encode()
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434
292
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435
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436
341
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437 def register_numbers(regs):
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438 for r in regs:
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439 yield r.num
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440
341
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441 class Pop(ThumbInstruction):
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442 def __init__(self, regs):
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443 assert type(regs) is set
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444 self.regs = regs
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445 self.token = ThumbToken()
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446
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447 def __repr__(self):
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448 return 'Pop {{{}}}'.format(self.regs)
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449
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450 def encode(self):
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451 for n in register_numbers(self.regs):
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452 if n < 8:
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453 self.token[n] = 1
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454 elif n == 15:
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455 self.token[8] = 1
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456 else:
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457 raise NotImplementedError('not implemented for this register')
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458 self.token[9:16] = 0x5E
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459 return self.token.encode()
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460
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461
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462
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463 class Yield(ThumbInstruction):
292
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464 def encode(self):
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465 return u16(0xbf10)
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466
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467 # misc:
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468
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469 # add/sub SP:
341
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470 class addspsp_base(ThumbInstruction):
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471 def __init__(self, imm7):
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472 self.imm7 = imm7
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473 assert self.imm7 % 4 == 0
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474 self.imm7 >>= 2
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475
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476 def encode(self):
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477 return u16((self.opcode << 7) | self.imm7)
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478
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479 def __repr__(self):
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480 mnemonic = self.__class__.__name__
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481 return '{} sp, sp, {}'.format(mnemonic, self.imm7 << 2)
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482
305
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483
292
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484 class AddSp(addspsp_base):
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485 opcode = 0b101100000
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486
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487
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488 class SubSp(addspsp_base):
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489 opcode = 0b101100001