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205
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1 import struct, types
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206
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2 from target import Register, Instruction, Target, Imm8, Label, Imm3
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3 from asmnodes import ASymbol, ANumber, AUnop, ABinop
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202
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4 from ppci import CompilerError
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205
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5 import ir
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202
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6
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218
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7 # TODO: encode this in DSL (domain specific language)
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8
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202
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9 def u16(h):
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10 return struct.pack('<H', h)
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11
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205
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12 def u32(x):
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13 return struct.pack('<I', x)
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14
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202
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15 armtarget = Target('arm')
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16
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17 class ArmReg(Register):
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18 def __init__(self, num, name):
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19 super().__init__(name)
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20 self.num = num
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206
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21 def __repr__(self):
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22 return self.name
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202
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23
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203
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24 class RegOp:
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25 def __init__(self, num):
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206
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26 assert num < 16
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203
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27 self.num = num
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28
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29 @classmethod
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30 def Create(cls, vop):
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31 if type(vop) is ASymbol:
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32 name = vop.name
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33 regs = {}
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34 for r in armtarget.registers:
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35 regs[r.name] = r
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36 if name in regs:
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37 r = regs[name]
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38 return cls(r.num)
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39
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206
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40 def getRegNum(n):
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41 for r in armtarget.registers:
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42 if r.num == n:
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43 return r
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203
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44
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206
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45 def getRegisterRange(n1, n2):
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46 regs = []
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47 if n1.num < n2.num:
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48 for n in range(n1.num, n2.num + 1):
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49 r = getRegNum(n)
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50 assert r
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51 regs.append(r)
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52 return regs
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203
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53
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212
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54 class MemoryOp:
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55 def __init__(self, basereg, offset):
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56 assert type(basereg) is ArmReg
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57 self.basereg = basereg
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58 self.offset = offset
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59
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60 @classmethod
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61 def Create(cls, vop):
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62 if type(vop) is AUnop and vop.operation == '[]':
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63 vop = vop.arg # descent
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64 if type(vop) is ABinop:
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65 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
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66 offset = vop.arg2.number
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67 basereg = RegOp.Create(vop.arg1)
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68 if not basereg:
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69 return
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70 else:
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71 return
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72 elif type(vop) is ASymbol:
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73 offset = 0
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74 basereg = RegOp.Create(vop)
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75 if not basereg:
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76 return
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77 else:
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78 return
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79 return cls(getRegNum(basereg.num), offset)
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80 pass
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81
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205
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82 class RegisterSet:
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83 def __init__(self, regs):
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206
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84 assert type(regs) is set
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85 self.regs = regs
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86 def __repr__(self):
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87 return ','.join([str(r) for r in self.regs])
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88 @classmethod
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89 def Create(cls, vop):
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90 assert type(vop) is AUnop and vop.operation == '{}'
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91 assert type(vop.arg) is list
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92 regs = set()
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93 for arg in vop.arg:
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94 if type(arg) is ASymbol:
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95 reg = RegOp.Create(arg)
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96 if not reg:
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97 return
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98 regs.add(reg)
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99 elif type(arg) is ABinop and arg.op == '-':
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100 reg1 = RegOp.Create(arg.arg1)
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101 reg2 = RegOp.Create(arg.arg2)
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102 if not reg1:
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103 return
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104 if not reg2:
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105 return
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106 for r in getRegisterRange(reg1, reg2):
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107 regs.add(r)
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108 else:
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109 raise Exception('Cannot be')
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110 return cls(regs)
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111
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112 def registerNumbers(self):
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113 return [r.num for r in self.regs]
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114
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202
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115 # 8 bit registers:
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205
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116 r0 = ArmReg(0, 'r0')
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117 armtarget.registers.append(r0)
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118 r1 = ArmReg(1, 'r1')
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119 armtarget.registers.append(r1)
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120 r2 = ArmReg(2, 'r2')
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121 armtarget.registers.append(r2)
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122 r3 = ArmReg(3, 'r3')
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123 armtarget.registers.append(r3)
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124 r4 = ArmReg(4, 'r4')
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125 armtarget.registers.append(r4)
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126 r5 = ArmReg(5, 'r5')
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127 armtarget.registers.append(r5)
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128 r6 = ArmReg(6, 'r6')
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129 armtarget.registers.append(r6)
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130 r7 = ArmReg(7, 'r7')
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131 armtarget.registers.append(r7)
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218
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132 r10 = ArmReg(10, 'r10')
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133 armtarget.registers.append(r10)
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134 r11 = ArmReg(11, 'r11')
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135 armtarget.registers.append(r11)
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206
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136 # Other registers:
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137 # TODO
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138 sp = ArmReg(13, 'sp')
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139 armtarget.registers.append(sp)
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140 lr = ArmReg(14, 'lr')
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141 armtarget.registers.append(lr)
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142 pc = ArmReg(15, 'pc')
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143 armtarget.registers.append(pc)
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202
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144
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145 class ArmInstruction(Instruction):
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146 pass
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147
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148 class ldr_ins(ArmInstruction):
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149 mnemonic = 'ldr'
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150 opcode = 1337
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151 irpattern = 'todo'
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152
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205
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153 class dcd_ins(ArmInstruction):
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154 mnemonic = 'dcd'
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155 def __init__(self, expr):
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156 self.expr = expr
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157 def encode(self):
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158 return u32(self.expr)
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202
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159
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160 @armtarget.instruction
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212
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161 class storeimm5_ins(ArmInstruction):
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162 """ str Rt, [Rn, imm5], store value into memory """
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163 mnemonic = 'str'
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164 operands = (RegOp, MemoryOp)
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165 def __init__(self, rt, memop):
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166 assert memop.offset % 4 == 0
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167 self.imm5 = memop.offset >> 2
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168 self.rn = memop.basereg.num
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169 self.rt = rt.num
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170
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171 def encode(self):
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172 Rn = self.rn
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173 Rt = self.rt
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174 imm5 = self.imm5
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175 h = (0xC << 11) | (imm5 << 6) | (Rn << 3) | Rt
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176 return u16(h)
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177
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178 @armtarget.instruction
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179 class loadimm5_ins(ArmInstruction):
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180 """ str Rt, [Rn, imm5], store value into memory """
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181 mnemonic = 'ldr'
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182 operands = (RegOp, MemoryOp)
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183 def __init__(self, rt, memop):
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184 assert memop.offset % 4 == 0
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185 self.imm5 = memop.offset >> 2
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186 self.rn = memop.basereg.num
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187 self.rt = rt.num
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188
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189 def encode(self):
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190 Rn = self.rn
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191 Rt = self.rt
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192 imm5 = self.imm5
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193 h = (0xD << 11) | (imm5 << 6) | (Rn << 3) | Rt
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194 return u16(h)
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195
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196 @armtarget.instruction
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202
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197 class mov_ins(ArmInstruction):
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198 """ mov Rd, imm8, move immediate value into register """
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199 mnemonic = 'mov'
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200 opcode = 4 # 00100 Rd(3) imm8
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201 operands = (RegOp, Imm8)
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205
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202 irpattern = ir.ImmLoad
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203
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203 def __init__(self, rd, imm):
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204 self.imm = imm.imm
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205 self.r = rd.num
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205
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206
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207 @classmethod
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208 def FromIr(cls, ir_ins):
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209 pass
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210
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202
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211 def encode(self):
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212 rd = self.r
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213 opcode = self.opcode
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214 imm8 = self.imm
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215 h = (opcode << 11) | (rd << 8) | imm8
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216 return u16(h)
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217
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203
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218 @armtarget.instruction
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219 class movregreg_ins(ArmInstruction):
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220 """ mov Rd, Rm """
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221 mnemonic = 'mov'
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222 opcode = 8 # 01000 Rd(3) imm8
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223 operands = (RegOp, RegOp)
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224 def __init__(self, rd, rm):
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225 self.rd = rd
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226 self.rm = rm
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227 def encode(self):
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228 rd = self.rd.num
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229 D = (rd & 0x8) >> 3
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230 assert D < 2
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231 rd = rd & 0x7
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232 rm = self.rm.num
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233 assert rm < 16
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234 opcode = self.opcode
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235 h = (opcode << 11) | (3 << 9) | (D << 7) | (rm << 3) | rd
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236 return u16(h)
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237
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238 @armtarget.instruction
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239 class addregregimm3_ins(ArmInstruction):
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240 """ add Rd, Rn, imm3 """
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241 mnemonic = 'add'
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242 opcode = 3 # 00011
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243 operands = (RegOp, RegOp, Imm3)
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205
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244 irpattern = 3
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203
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245 def __init__(self, rd, rn, imm3):
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246 self.rd = rd
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247 self.rn = rn
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248 self.imm3 = imm3
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249 def encode(self):
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250 rd = self.rd.num
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251 rn = self.rn.num
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252 imm3 = self.imm3.imm
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253 opcode = self.opcode
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254 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd
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255 return u16(h)
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256
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257 @armtarget.instruction
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258 class cmpregimm8_ins(ArmInstruction):
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259 """ cmp Rn, imm8 """
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260 mnemonic = 'cmp'
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261 opcode = 5 # 00101
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262 operands = (RegOp, Imm8)
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263 def __init__(self, rn, imm):
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264 self.rn = rn
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265 self.imm = imm
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266 def encode(self):
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267 rn = self.rn.num
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268 imm = self.imm.imm
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269 opcode = self.opcode
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270 h = (opcode << 11) | (rn << 8) | imm
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271 return u16(h)
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202
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272
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273 @armtarget.instruction
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218
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274 class cmp_ins(ArmInstruction):
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275 """ cmp Rn, Rm """
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276 mnemonic = 'cmp'
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277 operands = (RegOp, RegOp)
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278 def __init__(self, rn, rm):
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279 self.rn = rn
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280 self.rm = rm
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281 def encode(self):
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282 rn = self.rn.num
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283 rm = self.rm.num
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284 assert rn < 8
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285 assert rm < 8
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286 opcode = 0x42
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287 h = (opcode << 8) | (1 << 7) | (rm << 3) | (rn & 0x7)
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288 return u16(h)
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289
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290 @armtarget.instruction
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205
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291 class jmp_ins(ArmInstruction):
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206
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292 operands = (Label,)
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205
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293 mnemonic = 'jmp'
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294 def __init__(self, target_label):
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295 self.target = target_label
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296 def fixUp(self):
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297 pass
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298 def encode(self):
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299 h = 1337 # TODO
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300 return u16(h)
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301
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302 @armtarget.instruction
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303 class push_ins(ArmInstruction):
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206
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304 operands = (RegisterSet,)
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205
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305 mnemonic = 'push'
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306 def __init__(self, regs):
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206
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307 assert (type(regs),) == self.operands, (type(regs),)
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205
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308 self.regs = regs
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206
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309 def __repr__(self):
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310 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
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311 def encode(self):
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206
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312 reg_list = 0
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313 M = 0
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314 for n in self.regs.registerNumbers():
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315 if n < 8:
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316 reg_list |= (1 << n)
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317 elif n == 14:
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318 M = 1
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319 else:
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320 raise NotImplementedError('not implemented for this register')
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321 h = (0x5a << 9) | (M << 8) | reg_list
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322 return u16(h)
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205
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323
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324 @armtarget.instruction
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325 class pop_ins(ArmInstruction):
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206
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326 operands = (RegisterSet,)
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205
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327 mnemonic = 'pop'
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328 def __init__(self, regs):
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329 self.regs = regs
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207
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330 def __repr__(self):
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331 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
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332 def encode(self):
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206
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333 reg_list = 0
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334 P = 0
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335 for n in self.regs.registerNumbers():
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336 if n < 8:
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337 reg_list |= (1 << n)
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338 elif n == 15:
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339 P = 1
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340 else:
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341 raise NotImplementedError('not implemented for this register')
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342 h = (0x5E << 9) | (P << 8) | reg_list
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343 return u16(h)
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205
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344 return u16(0)
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345
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346 @armtarget.instruction
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202
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347 class yield_ins(ArmInstruction):
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348 operands = ()
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349 mnemonic = 'yield'
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350 def encode(self):
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351 return u16(0xbf10)
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352
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206
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353 armtarget.check()
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354
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