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322
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1
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2 from target.arminstructions import Orr, Lsl, Str2, Ldr2, Ldr3
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3 from target.arminstructions import B, Bl, Bgt, Blt, Beq, Bne
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4 from target.arminstructions import Mov2, Mov3
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5 from target.arminstructions import Add, Sub, Cmp, Sub2, Add2, Mul
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6
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7 %%
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8
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9 %terminal ADDI32 SUBI32 ORI32 SHLI32
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10 %terminal CONSTI32 MEMI32 REGI32 CALL
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11
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12 %%
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13
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14 reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add, dst=[d], src=[$1, $2]); return d .)
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15 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$1, $2]); return d .)
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16 reg: ORI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Orr, dst=[d], src=[$1, $2]); return d .)
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17 reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Lsl, dst=[d], src=[$1, $2]); return d .)
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18 reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Mul, dst=[d], src=[$1, $2]); return d .)
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19
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20 reg: CONSTI32 3 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$$.value]); return d .)
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21 reg: MEMI32(reg) 4 (. d = self.newTmp(); self.emit(Ldr2, dst=[d], src=[$1]); return d .)
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22 reg: REGI32 1 (. pass .)
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23 reg: CALL 1 (. pass .)
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24
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25
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