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205
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1 import struct, types
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206
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2 from target import Register, Instruction, Target, Imm8, Label, Imm3
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219
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3 from asmnodes import ASymbol, ANumber, AUnop, ABinop, ALabel
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202
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4 from ppci import CompilerError
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205
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5 import ir
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202
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6
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218
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7 # TODO: encode this in DSL (domain specific language)
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8
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202
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9 def u16(h):
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10 return struct.pack('<H', h)
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11
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205
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12 def u32(x):
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13 return struct.pack('<I', x)
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14
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202
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15 armtarget = Target('arm')
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16
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17 class ArmReg(Register):
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18 def __init__(self, num, name):
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19 super().__init__(name)
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20 self.num = num
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206
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21 def __repr__(self):
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22 return self.name
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202
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23
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203
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24 class RegOp:
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25 def __init__(self, num):
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206
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26 assert num < 16
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203
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27 self.num = num
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28
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29 @classmethod
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30 def Create(cls, vop):
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31 if type(vop) is ASymbol:
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32 name = vop.name
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33 regs = {}
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34 for r in armtarget.registers:
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35 regs[r.name] = r
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36 if name in regs:
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37 r = regs[name]
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38 return cls(r.num)
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219
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39
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40 class Reg8Op:
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41 def __init__(self, num):
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42 assert num < 8
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43 self.num = num
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44
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45 @classmethod
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46 def Create(cls, vop):
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47 if type(vop) is ASymbol:
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48 name = vop.name
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49 regs = {}
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50 for r in armtarget.registers:
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51 regs[r.name] = r
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52 if name in regs:
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53 r = regs[name]
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54 if r.num < 8:
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55 return cls(r.num)
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203
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56
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206
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57 def getRegNum(n):
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58 for r in armtarget.registers:
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59 if r.num == n:
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60 return r
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203
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61
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206
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62 def getRegisterRange(n1, n2):
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63 regs = []
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64 if n1.num < n2.num:
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65 for n in range(n1.num, n2.num + 1):
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66 r = getRegNum(n)
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67 assert r
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68 regs.append(r)
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69 return regs
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203
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70
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212
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71 class MemoryOp:
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72 def __init__(self, basereg, offset):
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73 assert type(basereg) is ArmReg
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74 self.basereg = basereg
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75 self.offset = offset
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76
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219
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77 def __repr__(self):
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78 return '[{}, #{}]'.format(self.basereg, self.offset)
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79
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212
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80 @classmethod
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81 def Create(cls, vop):
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82 if type(vop) is AUnop and vop.operation == '[]':
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83 vop = vop.arg # descent
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84 if type(vop) is ABinop:
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85 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
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86 offset = vop.arg2.number
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87 basereg = RegOp.Create(vop.arg1)
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88 if not basereg:
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89 return
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90 else:
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91 return
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92 elif type(vop) is ASymbol:
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93 offset = 0
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94 basereg = RegOp.Create(vop)
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95 if not basereg:
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96 return
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97 else:
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98 return
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99 return cls(getRegNum(basereg.num), offset)
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219
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100
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101 class MemoryOpReg8Imm5:
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102 def __init__(self, basereg, offset):
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103 assert type(basereg) is ArmReg
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104 self.basereg = basereg
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105 self.offset = offset
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106
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107 def __repr__(self):
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108 return '[{}, #{}]'.format(self.basereg, self.offset)
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109
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110 @classmethod
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111 def Create(cls, vop):
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112 if type(vop) is AUnop and vop.operation == '[]':
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113 vop = vop.arg # descent
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114 if type(vop) is ABinop:
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115 if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
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116 offset = vop.arg2.number
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117 if offset > 120:
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118 return
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119 basereg = Reg8Op.Create(vop.arg1)
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120 if not basereg:
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121 return
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122 else:
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123 return
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124 elif type(vop) is ASymbol:
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125 offset = 0
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126 basereg = Reg8Op.Create(vop)
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127 if not basereg:
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128 return
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129 else:
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130 return
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131 return cls(getRegNum(basereg.num), offset)
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212
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132
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205
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133 class RegisterSet:
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134 def __init__(self, regs):
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206
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135 assert type(regs) is set
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136 self.regs = regs
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137 def __repr__(self):
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138 return ','.join([str(r) for r in self.regs])
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139 @classmethod
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140 def Create(cls, vop):
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141 assert type(vop) is AUnop and vop.operation == '{}'
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142 assert type(vop.arg) is list
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143 regs = set()
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144 for arg in vop.arg:
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145 if type(arg) is ASymbol:
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146 reg = RegOp.Create(arg)
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147 if not reg:
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148 return
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149 regs.add(reg)
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150 elif type(arg) is ABinop and arg.op == '-':
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151 reg1 = RegOp.Create(arg.arg1)
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152 reg2 = RegOp.Create(arg.arg2)
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153 if not reg1:
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154 return
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155 if not reg2:
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156 return
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157 for r in getRegisterRange(reg1, reg2):
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158 regs.add(r)
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159 else:
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160 raise Exception('Cannot be')
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161 return cls(regs)
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162
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163 def registerNumbers(self):
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164 return [r.num for r in self.regs]
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165
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202
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166 # 8 bit registers:
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167 r0 = ArmReg(0, 'r0')
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168 armtarget.registers.append(r0)
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206
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169 r1 = ArmReg(1, 'r1')
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170 armtarget.registers.append(r1)
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171 r2 = ArmReg(2, 'r2')
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172 armtarget.registers.append(r2)
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173 r3 = ArmReg(3, 'r3')
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174 armtarget.registers.append(r3)
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202
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175 r4 = ArmReg(4, 'r4')
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176 armtarget.registers.append(r4)
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203
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177 r5 = ArmReg(5, 'r5')
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178 armtarget.registers.append(r5)
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179 r6 = ArmReg(6, 'r6')
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180 armtarget.registers.append(r6)
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181 r7 = ArmReg(7, 'r7')
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182 armtarget.registers.append(r7)
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206
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183 # Other registers:
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184 # TODO
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185 sp = ArmReg(13, 'sp')
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186 armtarget.registers.append(sp)
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187 lr = ArmReg(14, 'lr')
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188 armtarget.registers.append(lr)
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189 pc = ArmReg(15, 'pc')
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190 armtarget.registers.append(pc)
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202
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191
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192 class ArmInstruction(Instruction):
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193 pass
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194
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205
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195 class dcd_ins(ArmInstruction):
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196 mnemonic = 'dcd'
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197 def __init__(self, expr):
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198 self.expr = expr
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219
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199
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205
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200 def encode(self):
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201 return u32(self.expr)
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202
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202
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219
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203 def __repr__(self):
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204 return 'DCD 0x{0:X}'.format(self.expr)
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205
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206
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207
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208 # Memory related
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209
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210 class LS_imm5_base(ArmInstruction):
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211 """ ??? Rt, [Rn, imm5] """
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212 operands = (Reg8Op, MemoryOpReg8Imm5)
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212
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213 def __init__(self, rt, memop):
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214 assert memop.offset % 4 == 0
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215 self.imm5 = memop.offset >> 2
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216 self.rn = memop.basereg.num
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217 self.rt = rt.num
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219
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218 self.memloc = memop
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219 assert self.rn < 8
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220 assert self.rt < 8
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212
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221
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222 def encode(self):
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223 Rn = self.rn
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224 Rt = self.rt
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225 imm5 = self.imm5
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219
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226
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227 h = (self.opcode << 11) | (imm5 << 6) | (Rn << 3) | Rt
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228 return u16(h)
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229 def __repr__(self):
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230 return '{} {}, {}'.format(self.mnemonic, self.rt, self.memloc)
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231
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232 @armtarget.instruction
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233 class storeimm5_ins(LS_imm5_base):
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234 mnemonic = 'STR'
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235 opcode = 0xC
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236
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237 @armtarget.instruction
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238 class loadimm5_ins(LS_imm5_base):
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239 mnemonic = 'LDR'
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240 opcode = 0xD
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241
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242 class ls_sp_base_imm8(ArmInstruction):
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243 operands = (Reg8Op, MemoryOp)
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244 def __init__(self, rt, memop):
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245 self.rt = rt
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246 assert memop.basereg.num == 13
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247 self.offset = memop.offset
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248
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249 def encode(self):
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250 rt = self.rt.num
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251 assert rt < 8
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252 imm8 = self.offset >> 2
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253 assert imm8 < 256
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254 h = (self.opcode << 8) | (rt << 8) | imm8
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212
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255 return u16(h)
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256
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219
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257 def __repr__(self):
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258 return '{} {}, [sp,#{}]'.format(self.mnemonic, self.rt, self.offset)
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259
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212
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260 @armtarget.instruction
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219
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261 class ldr_pcrel(ArmInstruction):
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262 """ ldr Rt, [PC, imm8], store value into memory """
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212
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263 mnemonic = 'ldr'
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264 operands = (RegOp, MemoryOp)
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219
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265 def __init__(self, rt, label):
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266 self.rt = rt
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267 self.label = label
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268 self.offset = 0
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212
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269
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270 def encode(self):
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219
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271 rt = self.rt.num
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272 assert rt < 8
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273 imm8 = self.offset >> 2
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274 assert imm8 < 256
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275 h = (0x9 << 11) | (rt << 8) | imm8
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212
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276 return u16(h)
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277
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219
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278 def __repr__(self):
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279 return 'LDR {}, [pc,#{}]'.format(self.rt, self.offset)
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280
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281 @armtarget.instruction
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282 class ldr_sprel(ls_sp_base_imm8):
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283 """ ldr Rt, [SP, imm8] """
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284 mnemonic = 'LDR'
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285 opcode = 0x98
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286
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287 @armtarget.instruction
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288 class str_sprel(ls_sp_base_imm8):
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289 """ str Rt, [SP, imm8] """
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290 mnemonic = 'STR'
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291 opcode = 0x90
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292
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212
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293 @armtarget.instruction
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202
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294 class mov_ins(ArmInstruction):
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295 """ mov Rd, imm8, move immediate value into register """
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296 mnemonic = 'mov'
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203
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297 opcode = 4 # 00100 Rd(3) imm8
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298 operands = (RegOp, Imm8)
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205
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299 irpattern = ir.ImmLoad
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203
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300 def __init__(self, rd, imm):
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301 self.imm = imm.imm
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302 self.r = rd.num
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205
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303
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202
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304 def encode(self):
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305 rd = self.r
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306 opcode = self.opcode
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307 imm8 = self.imm
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308 h = (opcode << 11) | (rd << 8) | imm8
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309 return u16(h)
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219
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310 def __repr__(self):
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311 return 'MOV {0}, xx?'.format(self.r)
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202
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312
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203
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313 @armtarget.instruction
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314 class movregreg_ins(ArmInstruction):
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315 """ mov Rd, Rm """
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316 mnemonic = 'mov'
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317 operands = (RegOp, RegOp)
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318 def __init__(self, rd, rm):
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319 self.rd = rd
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320 self.rm = rm
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321 def encode(self):
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322 rd = self.rd.num
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323 D = (rd & 0x8) >> 3
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324 assert D < 2
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325 rd = rd & 0x7
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326 rm = self.rm.num
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327 assert rm < 16
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328 opcode = self.opcode
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219
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329 h = (1 << 14) | (3 << 9) | (D << 7) | (rm << 3) | rd
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203
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330 return u16(h)
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331
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219
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332
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333
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334 # Arithmatics:
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335
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203
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336 @armtarget.instruction
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337 class addregregimm3_ins(ArmInstruction):
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338 """ add Rd, Rn, imm3 """
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339 mnemonic = 'add'
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340 opcode = 3 # 00011
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341 operands = (RegOp, RegOp, Imm3)
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205
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342 irpattern = 3
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203
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343 def __init__(self, rd, rn, imm3):
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344 self.rd = rd
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345 self.rn = rn
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346 self.imm3 = imm3
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347 def encode(self):
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348 rd = self.rd.num
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349 rn = self.rn.num
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350 imm3 = self.imm3.imm
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351 opcode = self.opcode
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352 h = (opcode << 11) | (1 << 10) | (imm3 << 6) | (rn << 3) | rd
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353 return u16(h)
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354
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219
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355 class regregreg_base(ArmInstruction):
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356 """ ??? Rd, Rn, Rm """
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357 operands = (Reg8Op, Reg8Op, Reg8Op)
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358 def __init__(self, rd, rn, rm):
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359 self.rd = rd
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360 self.rn = rn
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361 self.rm = rm
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362 def encode(self):
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363 rd = self.rd.num
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364 rn = self.rn.num
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365 rm = self.rm.num
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366 h = (self.opcode << 9) | (rm << 6) | (rn << 3) | rd
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367 return u16(h)
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368 def __repr__(self):
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369 return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
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370
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371 @armtarget.instruction
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372 class addregs_ins(regregreg_base):
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373 mnemonic = 'ADD'
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374 opcode = 0b0001100
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375
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376 @armtarget.instruction
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377 class subregs_ins(regregreg_base):
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378 mnemonic = 'SUB'
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379 opcode = 0b0001101
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380
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381 class regreg_base(ArmInstruction):
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382 """ ??? Rdn, Rm """
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383 operands = (Reg8Op, Reg8Op)
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384 def __init__(self, rdn, rm):
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385 self.rdn = rdn
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386 self.rm = rm
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387 def encode(self):
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388 rdn = self.rdn.num
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389 rm = self.rm.num
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390 h = (self.opcode << 6) | (rm << 3) | rdn
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391 return u16(h)
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392 def __repr__(self):
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393 return '{} {}, {}'.format(self.mnemonic, self.rdn, self.rm)
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394
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395 @armtarget.instruction
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396 class andregs_ins(regreg_base):
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397 mnemonic = 'AND'
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398 opcode = 0b0100000000
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399
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400 @armtarget.instruction
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401 class orrregs_ins(regreg_base):
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402 mnemonic = 'ORR'
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403 opcode = 0b0100001100
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404
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405 @armtarget.instruction
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406 class cmp_ins(regreg_base):
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407 mnemonic = 'CMP'
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408 opcode = 0b0100001010
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409
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203
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410 @armtarget.instruction
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411 class cmpregimm8_ins(ArmInstruction):
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412 """ cmp Rn, imm8 """
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413 mnemonic = 'cmp'
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414 opcode = 5 # 00101
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415 operands = (RegOp, Imm8)
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416 def __init__(self, rn, imm):
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417 self.rn = rn
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418 self.imm = imm
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419 def encode(self):
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420 rn = self.rn.num
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421 imm = self.imm.imm
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422 opcode = self.opcode
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423 h = (opcode << 11) | (rn << 8) | imm
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424 return u16(h)
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202
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425
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219
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426 # Jumping:
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218
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427
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428 @armtarget.instruction
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205
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429 class jmp_ins(ArmInstruction):
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219
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430 operands = (ALabel,)
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205
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431 mnemonic = 'jmp'
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432 def __init__(self, target_label):
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219
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433 assert type(target_label) is ALabel
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205
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434 self.target = target_label
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435 def fixUp(self):
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436 pass
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437 def encode(self):
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219
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438 h = 0 # TODO
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205
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439 return u16(h)
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219
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440 def __repr__(self):
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441 return 'B {0}'.format(self.target.name)
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442
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443 @armtarget.instruction
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444 class beq_ins(ArmInstruction):
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445 operands = (ALabel,)
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446 mnemonic = 'beq'
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447 def __init__(self, target_label):
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448 assert type(target_label) is ALabel
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449 self.target = target_label
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450 def fixUp(self):
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451 pass
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452 def encode(self):
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453 h = 0 # TODO
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454 return u16(h)
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455 def __repr__(self):
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456 return 'BEQ {0}'.format(self.target.name)
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205
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457
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458 @armtarget.instruction
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459 class push_ins(ArmInstruction):
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206
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460 operands = (RegisterSet,)
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205
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461 mnemonic = 'push'
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462 def __init__(self, regs):
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206
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463 assert (type(regs),) == self.operands, (type(regs),)
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205
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464 self.regs = regs
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206
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465 def __repr__(self):
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466 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
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205
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467 def encode(self):
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206
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468 reg_list = 0
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469 M = 0
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470 for n in self.regs.registerNumbers():
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471 if n < 8:
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472 reg_list |= (1 << n)
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473 elif n == 14:
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474 M = 1
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475 else:
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476 raise NotImplementedError('not implemented for this register')
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477 h = (0x5a << 9) | (M << 8) | reg_list
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478 return u16(h)
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205
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479
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480 @armtarget.instruction
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481 class pop_ins(ArmInstruction):
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206
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482 operands = (RegisterSet,)
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205
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483 mnemonic = 'pop'
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484 def __init__(self, regs):
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485 self.regs = regs
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207
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486 def __repr__(self):
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487 return '{0} {{{1}}}'.format(self.mnemonic, self.regs)
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205
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488 def encode(self):
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206
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489 reg_list = 0
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490 P = 0
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491 for n in self.regs.registerNumbers():
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492 if n < 8:
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493 reg_list |= (1 << n)
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494 elif n == 15:
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495 P = 1
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496 else:
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497 raise NotImplementedError('not implemented for this register')
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498 h = (0x5E << 9) | (P << 8) | reg_list
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499 return u16(h)
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|
205
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500
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501 @armtarget.instruction
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202
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502 class yield_ins(ArmInstruction):
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503 operands = ()
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504 mnemonic = 'yield'
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505 def encode(self):
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506 return u16(0xbf10)
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507
|
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206
|
508 armtarget.check()
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509
|
