--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/python/disasm.py	Thu Nov 28 20:39:56 2013 +0100
@@ -0,0 +1,50 @@
+from PyQt4.QtCore import *
+from PyQt4.QtGui import *
+
+
+class DisAsmModel(QAbstractTableModel):
+    def __init__(self):
+        super().__init__()
+        self.outs = None
+        self.instructions = []
+        self.headers = ['Address', 'Bytes', 'Instruction']
+        self.txts = []
+        self.txts.append(lambda i: '0x{:08x}'.format(i.address))
+        self.txts.append(lambda i: str(i.encode()))
+        self.txts.append(lambda i: str(i))
+
+    def rowCount(self, parent):
+        return len(self.instructions)
+        
+    def columnCount(self, parent):
+        return len(self.headers)
+
+    def data(self, index, role):
+        if not index.isValid():
+            return
+        row, col = index.row(), index.column()
+        if role == Qt.DisplayRole:
+            i = self.instructions[row]
+            return self.txts[col](i)
+
+    def headerData(self, section, orientation, role):
+        if orientation == Qt.Horizontal and role == Qt.DisplayRole:
+            return self.headers[section]
+            
+    def setInstructions(self, ins):
+        self.instructions = ins
+        self.modelReset.emit()
+    
+
+class Disassembly(QTableView):
+    def __init__(self):
+        super().__init__()
+        self.dm = DisAsmModel()
+        self.setModel(self.dm)
+
+    def showPos(self, p):
+        for i in self.dm.instructions:
+            if i.address == p:
+                row = self.dm.instructions.index(i)
+                self.selectRow(row)
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/python/target/openrisc.py	Thu Nov 28 20:39:56 2013 +0100
@@ -0,0 +1,4 @@
+
+
+import target
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/python/target/target_x86.py	Thu Nov 28 20:39:56 2013 +0100
@@ -0,0 +1,66 @@
+from target import Register, Instruction, Target
+
+class x86Register(Register):
+   def __init__(self, name):
+      self.name = name
+
+class REG16(x86Register):
+   pass
+
+def addRegs(cls, names):
+   for name in names:
+      r = cls(name)
+      globals()[name] = r
+
+addRegs(REG16, ['ax', 'bx', 'cx'])
+
+regs = """
+ax; reg16
+"""
+
+class MO:
+   def __init__(self):
+      pass
+
+instrs = """
+add; 0x0; mem8/reg8; reg8
+"""
+
+# machine op table:
+mot = []
+
+for i in instrs.split('\n'):
+   i = i.strip()
+   if i:
+      print('INS:', i)
+      mnemonic, opcode, op1, op2 = [a.strip() for a in i.split(';')]
+      print(op1.split('/'), op2.split('/'))
+
+
+print(mot)
+
+# Test first with these 3 instructions:
+"""
+mov reg64, reg64 : opcode=0x89
+xor reg64, reg64 : opcode=0x31
+inc reg64 : opcode=0xff
+"""
+
+class x86Machine:
+   def __init__(self):
+      self.table = []
+      self.table.append((0x0, 'add', 'reg8/mem8, reg8'))
+      self.table.append((0x1, 'add', 'reg16/mem16/reg32/mem32, reg16/reg32'))
+      self.table.append((0x2, 'add', 'reg8, reg8/mem8'))
+   def forMnemonic(self, m):
+      return [i for i in self.table if i[1] == m]
+   def emit(self, m, ops):
+      print(m, ops)
+      ops = self.forMnemonic(m)
+      print(ops)
+
+
+if __name__ == '__main__':
+   m = x86Machine()
+   m.emit('add', [ax, cx])
+   m.emit('mov', [bx, 1337])