Mercurial > lcfOS

changeset 365:98ff43cfdd36

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Nasty bug in adr instruction
author Windel Bouwman
date Wed, 19 Mar 2014 22:32:04 +0100
parents c49459768aaa
children 39bf68bf1891
files kernel/src/kernel.c3 python/ppci/bitfun.py python/ppci/linker.py python/ppci/target/arm/instructions.py util/test_patterns.txt
diffstat 5 files changed, 24 insertions(+), 19 deletions(-) [+]
line wrap: on
line diff
--- a/kernel/src/kernel.c3	Wed Mar 19 20:24:03 2014 +0100
+++ b/kernel/src/kernel.c3	Wed Mar 19 22:32:04 2014 +0100
@@ -20,12 +20,13 @@
     G = 0;
     arch.init();
 
-    do();
     io.println("Welcome to lcfos!");
 
     do();
     do();
     do();
+    io.println("Welcome 2!");
+    do();
     do();
 
     io.print_int(0x1337);
@@ -35,13 +36,13 @@
     var int a;
     for (a = 0; a < 2; a = a + 1)
     {
-      //io.print2("a = ", a);
+      io.print2("a = ", a);
     }
 
     io.print2("PFR0 = ", arch.pfr0());
     io.print2("PFR1 = ", arch.pfr1());
     io.print2("MMFR0 = ", arch.mmfr0());
-    io.print2("MPUIR = ", arch.mpuir());
+    // io.print2("MPUIR = ", arch.mpuir());
 
     // process.init();
     //memory:init();
--- a/python/ppci/bitfun.py	Wed Mar 19 20:24:03 2014 +0100
+++ b/python/ppci/bitfun.py	Wed Mar 19 22:32:04 2014 +0100
@@ -11,4 +11,15 @@
     assert n < 32
     return rotate_right(v, 32 - n)
 
+def encode_imm32(v):
+    """ Bundle 32 bit value into 4 bits rotation and 8 bits value
+     """
+    for i in range(0, 16):
+        v2 = rotate_left(v, i*2)
+        if (v2 & 0xFFFFFF00) == 0:
+            rotation = i
+            val = v2 & 0xFF
+            x = (rotation << 8) | val
+            return x
+    raise Exception("Invalid value {}".format(v))
 
--- a/python/ppci/linker.py	Wed Mar 19 20:24:03 2014 +0100
+++ b/python/ppci/linker.py	Wed Mar 19 22:32:04 2014 +0100
@@ -2,6 +2,7 @@
 import struct
 from .objectfile import ObjectFile
 from . import CompilerError
+from .bitfun import encode_imm32
 
 def align(x, m):
     while ((x % m) != 0):
@@ -99,7 +100,7 @@
         offset = -offset
         U = 0
     assert offset < 4096
-    section.data[reloc.offset+2] |= (U << 7) #(rel24 >> 16) & 0xFF
+    section.data[reloc.offset+2] |= (U << 7)
     section.data[reloc.offset+1] |= (offset >> 8) & 0xF
     section.data[reloc.offset+0] = offset & 0xFF
 
@@ -113,6 +114,7 @@
         offset = -offset
         U = 1
     assert offset < 4096
+    offset = encode_imm32(offset)
     section.data[reloc.offset+2] |= (U << 6)
     section.data[reloc.offset+1] |= (offset >> 8) & 0xF
     section.data[reloc.offset+0] = offset & 0xFF
--- a/python/ppci/target/arm/instructions.py	Wed Mar 19 20:24:03 2014 +0100
+++ b/python/ppci/target/arm/instructions.py	Wed Mar 19 22:32:04 2014 +0100
@@ -1,22 +1,11 @@
 
 from ..basetarget import Instruction, LabelAddress
-from ...bitfun import rotate_left
+from ...bitfun import encode_imm32
 
 from .token import ArmToken
 from .registers import R0, SP, ArmRegister
 
 
-def encode_imm32(v):
-    """ Bundle 32 bit value into 4 bits rotation and 8 bits value
-     """
-    for i in range(0, 16):
-        v2 = rotate_left(v, i*2)
-        if (v2 & 0xFFFFFF00) == 0:
-            rotation = i
-            val = v2 & 0xFF
-            x = (rotation << 8) | val
-            return x
-    raise Exception("Invalid value {}".format(v))
 
 # Instructions:
 
--- a/util/test_patterns.txt	Wed Mar 19 20:24:03 2014 +0100
+++ b/util/test_patterns.txt	Wed Mar 19 22:32:04 2014 +0100
@@ -42,6 +42,8 @@
 adr r1, cval
 pop {r2}
 ===
+adr r3, pc, #1024
+===
 lsl r11, r5, r3
 lsl r4, r8, r6
 ===
@@ -57,7 +59,7 @@
 mrc p15, 0, r1, c2, c0, 0
 mrc p14, 0, r1, c8, c7, 0
 ===
-mov sp, =a
-a:
-.word 0
+; mov sp, =a
+; a:
+; .word 0