# HG changeset patch
# User Windel Bouwman
# Date 1373385555 -7200
# Node ID 5af52987f5bd96288d92e90bc764416db43a4a0b
# Parent  85c8105318e766c51fc2bb189855aada7e7c2af1
Fixup of pc rel operand

diff -r 85c8105318e7 -r 5af52987f5bd python/cortexm3.py
--- a/python/cortexm3.py	Tue Jul 09 17:42:52 2013 +0200
+++ b/python/cortexm3.py	Tue Jul 09 17:59:15 2013 +0200
@@ -68,55 +68,39 @@
             regs.append(r)
     return regs
 
-class MemoryOp:
-    def __init__(self, basereg, offset):
-        assert type(basereg) is ArmReg
-        self.basereg = basereg
+def isRegOffset(regname, x, y):
+    if type(x) is ASymbol and type(y) is ANumber and x.name.upper() == regname:
+        return y.number
+    elif type(y) is ASymbol and type(x) is ANumber and y.name.upper() == regname:
+        return x.number
+    
+
+class MemRegXRel:
+    def __init__(self, offset):
+        assert offset % 4 == 0
         self.offset = offset
 
     def __repr__(self):
-        return '[{}, #{}]'.format(self.basereg, self.offset)
+        return '[{}, #{}]'.format(self.regname, self.offset)
 
     @classmethod
     def Create(cls, vop):
         if type(vop) is AUnop and vop.operation == '[]':
             vop = vop.arg # descent
-            if type(vop) is ABinop:
-                if vop.op == '+' and type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber:
-                    offset = vop.arg2.number
-                    basereg = RegOp.Create(vop.arg1)
-                    if not basereg:
-                        return
-                else:
-                    return
-            elif type(vop) is ASymbol:
-                offset = 0
-                basereg = RegOp.Create(vop)
-                if not basereg:
-                    return
-            else:
-                return
-            return cls(getRegNum(basereg.num), offset)
-
-class MemSpRel:
-    def __init__(self, offset):
-        assert offset % 4 == 0
-        self.offset = offset
-
-    def __repr__(self):
-        return '[sp, #{}]'.format(self.offset)
-
-    @classmethod
-    def Create(cls, vop):
-        if type(vop) is AUnop and vop.operation == '[]':
-            vop = vop.arg # descent
-            if type(vop) is ABinop and vop.op == '+':
-                if type(vop.arg1) is ASymbol and type(vop.arg2) is ANumber and vop.arg1.name.upper() == 'SP' and vop.arg2.number % 4 == 0:
+            offset = isRegOffset(cls.regname, vop.arg1, vop.arg2)
+            if type(offset) is int:
+                if offset % 4 == 0:
                     offset = vop.arg2.number
                     return cls(offset)
-            elif type(vop) is ASymbol and vop.name.upper() == 'SP':
+            elif type(vop) is ASymbol and vop.name.upper() == self.regname:
                 return cls(0)
 
+class MemSpRel(MemRegXRel):
+    regname = 'SP'
+
+class MemPcRel(MemRegXRel):
+    regname = 'PC'
+
 class MemoryOpReg8Imm5:
     def __init__(self, basereg, offset):
         assert type(basereg) is ArmReg
@@ -259,16 +243,16 @@
     opcode = 0xD
 
 class ls_sp_base_imm8(ArmInstruction):
-    operands = (Reg8Op, MemoryOp)
+    operands = (Reg8Op, MemSpRel)
     def __init__(self, rt, memop):
         self.rt = rt
-        assert memop.basereg.num == 13
         self.offset = memop.offset
 
     def encode(self):
         rt = self.rt.num
         assert rt < 8
         imm8 = self.offset >> 2
+        print(imm8)
         assert imm8 < 256
         h = (self.opcode << 8) | (rt << 8) | imm8
         return u16(h)
@@ -280,7 +264,7 @@
 class ldr_pcrel(ArmInstruction):
     """ ldr Rt, [PC, imm8], store value into memory """
     mnemonic = 'ldr'
-    operands = (RegOp, MemoryOp)
+    operands = (RegOp, MemPcRel)
     def __init__(self, rt, label):
         self.rt = rt
         self.label = label
diff -r 85c8105318e7 -r 5af52987f5bd python/testasm.py
--- a/python/testasm.py	Tue Jul 09 17:42:52 2013 +0200
+++ b/python/testasm.py	Tue Jul 09 17:59:15 2013 +0200
@@ -186,12 +186,10 @@
         self.feed('ldr r4, [r0 + 0]')
         self.check('0468')
 
-    @unittest.skip
     def testLdrSpRel(self):
         self.feed('ldr r0, [sp + 4]')
         self.check('0198')
 
-    @unittest.skip
     def testStrSpRel(self):
         self.feed('str r0, [sp + 4]')
         self.check('0190')