# HG changeset patch
# User Windel Bouwman
# Date 1394798536 -3600
# Node ID 52492b304adfb942a7b53f25ff1bd81b5d0e9f58
# Parent  c2ddc8a36f5e9aaa20b8fa153f1da0c6b175ff1f
Added newline to print

diff -r c2ddc8a36f5e -r 52492b304adf kernel/io.c3
--- a/kernel/io.c3	Fri Mar 14 10:30:13 2014 +0100
+++ b/kernel/io.c3	Fri Mar 14 13:02:16 2014 +0100
@@ -1,6 +1,12 @@
 module io;
 import arch;
 
+function void println(string txt)
+{
+    print(txt);
+    arch.putc(10); // Newline!
+}
+
 function void print(string txt)
 {
     var int i;
@@ -13,12 +19,35 @@
     }
 }
 
+// Print integer in hexadecimal notation:
 function void print_int(int i)
 {
+    print("0x");
+
     // int txt[20];
-    while (i != 0)
+    var int b;
+    var int c;
+    var int d;
+    d = 12;
+
+    for (b = 28; b > 0; b = b - 4)
     {
-        arch.putc(1);
+        //c = 7; // (i >> b) & 0xF;
+        d = b;
+        c = (i >> d) & 0xF;
+        // c = (i >> b) & 0xF;
+        if (c < 10)
+        {
+            arch.putc( 48 + c );
+        }
+        else
+        {
+            arch.putc( 65 - 10 + c );
+        }
+        // arch.putc( 65 );
+
     }
+
+    println("");
 }
 
diff -r c2ddc8a36f5e -r 52492b304adf kernel/kernel.c3
--- a/kernel/kernel.c3	Fri Mar 14 10:30:13 2014 +0100
+++ b/kernel/kernel.c3	Fri Mar 14 13:02:16 2014 +0100
@@ -11,11 +11,12 @@
 {
     arch.init();
 
-    io.print("Welcome to lcfos!");
+    io.println("Welcome to lcfos!");
+
+    // io.print_int(0x1337);
     process.init();
     //memory:init();
 
-
     //Process proc = new process:Process();
 
     //scheduler:queue(proc);
diff -r c2ddc8a36f5e -r 52492b304adf python/ppci/ir2tree.py
--- a/python/ppci/ir2tree.py	Fri Mar 14 10:30:13 2014 +0100
+++ b/python/ppci/ir2tree.py	Fri Mar 14 13:02:16 2014 +0100
@@ -15,7 +15,7 @@
 @register(ir.Binop)
 def binop_to_tree(e):
     names = {'+':'ADDI32', '-':'SUBI32', '|':'ORI32', '<<':'SHLI32',
-        '*':'MULI32'}
+        '*':'MULI32', '&':'ANDI32', '>>':'SHRI32'}
     op = names[e.operation]
     return Tree(op, makeTree(e.a), makeTree(e.b))
 
diff -r c2ddc8a36f5e -r 52492b304adf python/ppci/target/arm/__init__.py
--- a/python/ppci/target/arm/__init__.py	Fri Mar 14 10:30:13 2014 +0100
+++ b/python/ppci/target/arm/__init__.py	Fri Mar 14 13:02:16 2014 +0100
@@ -5,6 +5,7 @@
 from ..arm.registers import register_range
 
 from .instructions import Dcd, Mov, Add, Sub, Orr1, Mul, Mov2, Add1, Mul1
+from .instructions import Lsr1, Lsl1, And1, Sub1
 from .instructions import B, Bl, Ble, Bgt, Beq, Blt, Cmp, Cmp2
 from .instructions import Push, Pop, Str, Ldr, Ldr3, Str1, Ldr1, Adr
 from .selector import ArmInstructionSelector
@@ -24,7 +25,10 @@
         self.add_lowering(Mov2, lambda im: Mov2(im.dst[0], im.src[0]))
         self.add_lowering(Cmp2, lambda im: Cmp2(im.src[0], im.src[1]))
         self.add_lowering(Add1, lambda im: Add1(im.dst[0], im.src[0], im.src[1]))
+        self.add_lowering(Sub1, lambda im: Sub1(im.dst[0], im.src[0], im.src[1]))
         self.add_lowering(Mul1, lambda im: Mul1(im.dst[0], im.src[0], im.src[1]))
+        self.add_lowering(Lsr1, lambda im: Lsr1(im.dst[0], im.src[0], im.src[1]))
+        self.add_lowering(And1, lambda im: And1(im.dst[0], im.src[0], im.src[1]))
 
     def make_parser(self):
         # Assembly grammar:
@@ -99,6 +103,18 @@
         self.add_instruction(['orr', 'reg', ',', 'reg', ',', 'reg'],
                 lambda rhs: Orr1(rhs[1], rhs[3], rhs[5]))
 
+        self.add_keyword('and')
+        self.add_instruction(['and', 'reg', ',', 'reg', ',', 'reg'],
+                lambda rhs: And1(rhs[1], rhs[3], rhs[5]))
+
+        self.add_keyword('lsr')
+        self.add_instruction(['lsr', 'reg', ',', 'reg', ',', 'reg'],
+                lambda rhs: Lsr1(rhs[1], rhs[3], rhs[5]))
+
+        self.add_keyword('lsl')
+        self.add_instruction(['lsl', 'reg', ',', 'reg', ',', 'reg'],
+                lambda rhs: Lsl1(rhs[1], rhs[3], rhs[5]))
+
 
         # Jumping:
         self.add_keyword('b')
diff -r c2ddc8a36f5e -r 52492b304adf python/ppci/target/arm/arm.brg
--- a/python/ppci/target/arm/arm.brg	Fri Mar 14 10:30:13 2014 +0100
+++ b/python/ppci/target/arm/arm.brg	Fri Mar 14 13:02:16 2014 +0100
@@ -1,11 +1,12 @@
 
 from ppci.target.arm.instructions import Add1, Sub1, Mul1
 from ppci.target.arm.instructions import Ldr1, Ldr3, Adr
+from ppci.target.arm.instructions import And1, Lsr1, Lsl1
 
 %%
 
 %terminal ADDI32 SUBI32 MULI32 ADR
-%terminal ORI32 SHLI32
+%terminal ORI32 SHLI32 SHRI32 ANDI32
 %terminal CONSTI32 CONSTDATA MEMI32 REGI32 CALL
 %terminal MOVI32
 
@@ -14,6 +15,8 @@
 reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add1, dst=[d], src=[$1, $2]); return d .)
 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub1, dst=[d], src=[$1, $2]); return d .)
 reg: MULI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Mul1, dst=[d], src=[$1, $2]); return d .)
+reg: ANDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(And1, dst=[d], src=[$1, $2]); return d .)
+reg: SHRI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Lsr1, dst=[d], src=[$1, $2]); return d .)
 
 reg: MEMI32(ADDI32(reg, cn)) 2 (. d = self.newTmp(); self.emit(Ldr1, dst=[d], src=[$1], others=[$2]); return d .)
 reg: MEMI32(reg) 2 (. d = self.newTmp(); self.emit(Ldr1, dst=[d], src=[$1], others=[0]); return d .)
diff -r c2ddc8a36f5e -r 52492b304adf python/ppci/target/arm/instructions.py
--- a/python/ppci/target/arm/instructions.py	Fri Mar 14 10:30:13 2014 +0100
+++ b/python/ppci/target/arm/instructions.py	Fri Mar 14 13:02:16 2014 +0100
@@ -229,6 +229,43 @@
     opcode = 0b0001100
 
 
+class And1(OpRegRegReg):
+    mnemonic = 'AND'
+    opcode = 0b0000000
+
+
+class ShiftBase(ArmInstruction):
+    """ ? rd, rn, rm """
+    def __init__(self, rd, rn, rm):
+        super().__init__()
+        self.rd = rd
+        self.rn = rn
+        self.rm = rm
+
+    def encode(self):
+        self.token[0:4] = self.rn.num
+        self.token[4:8] = self.opcode
+        self.token[8:12] = self.rm.num
+        self.token[12:16] = self.rd.num
+        self.token.S = 0 # Set flags
+        self.token[21:28] = 0b1101
+        self.token.cond = 0xE # Always!
+        return self.token.encode()
+
+    def __repr__(self):
+        return '{} {}, {}, {}'.format(self.mnemonic, self.rd, self.rn, self.rm)
+
+
+class Lsr1(ShiftBase):
+    mnemonic = 'LSR'
+    opcode = 0b0011
+
+
+class Lsl1(ShiftBase):
+    mnemonic = 'LSL'
+    opcode = 0b0001
+
+
 class OpRegRegImm(ArmInstruction):
     """ add rd, rn, imm12 """
     def __init__(self, rd, rn, imm):
diff -r c2ddc8a36f5e -r 52492b304adf test/testarmasm.py
--- a/test/testarmasm.py	Fri Mar 14 10:30:13 2014 +0100
+++ b/test/testarmasm.py	Fri Mar 14 13:02:16 2014 +0100
@@ -41,10 +41,25 @@
         self.feed('sub r0, r1, 0x80000001')
         self.check('060141e2')
 
+    def testAnd1(self):
+        self.feed('and r9, r0, r2')
+        self.feed('and r4, r8, r6')
+        self.check('029000e0 064008e0')
+
     def testOrr1(self):
         self.feed('orr r8, r7, r6')
         self.check('068087e1')
 
+    def testLsl(self):
+        self.feed('lsl r11, r5, r3')
+        self.feed('lsl r4, r8, r6')
+        self.check('15b3a0e1 1846a0e1')
+
+    def testLsr(self):
+        self.feed('lsr r9, r0, r2')
+        self.feed('lsr r4, r8, r6')
+        self.check('3092a0e1 3846a0e1')
+
     def testBranches(self):
         self.feed('b sjakie')
         self.feed('ble sjakie')
diff -r c2ddc8a36f5e -r 52492b304adf test/testemulation.py
--- a/test/testemulation.py	Fri Mar 14 10:30:13 2014 +0100
+++ b/test/testemulation.py	Fri Mar 14 13:02:16 2014 +0100
@@ -81,7 +81,7 @@
         recipe = os.path.join(testdir, '..', 'kernel', 'arm.yaml')
         self.buildRecipe(recipe)
         data = runQemu('../kernel/kernel_arm.bin', machine='vexpress-a9')
-        self.assertEqual('Welcome to lcfos!', data)
+        self.assertEqual('Welcome to lcfos!\n', data)
 
 
 if __name__ == '__main__':
diff -r c2ddc8a36f5e -r 52492b304adf util/test_patterns.txt
--- a/util/test_patterns.txt	Fri Mar 14 10:30:13 2014 +0100
+++ b/util/test_patterns.txt	Fri Mar 14 13:02:16 2014 +0100
@@ -37,3 +37,12 @@
 adr r12, cval
 adr r1, cval
 pop {r2}
+===
+lsl r11, r5, r3
+lsl r4, r8, r6
+===
+lsr r9, r0, r2
+lsr r4, r8, r6
+===
+and r9, r0, r2
+and r4, r8, r6