view python/target/armv7.lidl @ 340:c7cc54c0dfdf devel

Test featurebranch
author Windel Bouwman
date Sun, 23 Feb 2014 16:24:01 +0100
parents 44f336460c2a
children
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#  This file specifies the encoding of the arm instruction set.

fields {
    word16 16 {
        opcode 15:12
        top2 15:14
        top6 15:10
        data_opcode 9..6
        opB 11:9
        Rm 8:6
        Rn 5:3
        Rt 2:0
    }
}

patterns {
 add = 0
 sub, mul = 1..2
 [r1, r2, r3, r4, r5] is todo = 1..5
 [STR, STRH, STRB, LDRSB, LDR, LDRH, LDRB, LDRSH] is opcode = 0b0101 & opB = {0 to 7}

 EQ, NE, CS, CC, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL = 0..14
 [AND, EOR, LSL, LSR, ASR, ADC, SBC, ROR, TST, RSB, CMP, CMN, ORR, MUL, BIC, MVN] is  0..15

 memop is STR | STRH | STRB | LDRSB | LDR | LDR | LDRH | LDRB | LDRSH
}


constructors
{
 alu rs1, reg_or_imm, rd
 memop Rt, [Rn, Rm] is memop & Rt & Rn & Rm
}