view test/sample4.brg @ 395:3b0c495e3008

Speed improvements
author Windel Bouwman
date Fri, 23 May 2014 14:28:03 +0200
parents 818be710e13d
children
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%%

%terminal ADDI ADDRLP ASGNI
%terminal CNSTI CVCI IOI INDIRC

%%

stmt: ASGNI(disp, reg) 1 'self.tr(1) '
stmt: reg 0 ' self.tr(2)'
reg: ADDI(reg, rc) 1 'self.tr(3) '
reg: CVCI(INDIRC(disp)) 1 'self.tr(4) '
reg: IOI 0 'self.tr(5)'
reg: disp 1 'self.tr(6)'
disp: ADDI(reg, con) 1 'self.tr(7)'
disp: ADDRLP 0 ' self.tr(8)'
rc: con 0    ' self.tr(9)'
rc: reg 0    'self.tr(10)'
con: CNSTI 0 ' self.tr(11)'
con: IOI 0   ' self.tr(12)'