diff python/zcc.py @ 205:d77cb5962cc5

Added some handcoded arm code generation
author Windel Bouwman
date Sun, 23 Jun 2013 18:23:18 +0200
parents de3a68f677a5
children 8b2f20aae086
line wrap: on
line diff
--- a/python/zcc.py	Fri Jun 21 15:01:08 2013 +0200
+++ b/python/zcc.py	Sun Jun 23 18:23:18 2013 +0200
@@ -1,13 +1,19 @@
 #!/usr/bin/python
 
 import sys, os, argparse
-import c3, ppci
+import c3, ppci, codegen
+import arm_cm3
+import codegenarm
+import outstream
 
+# Parse arguments:
 parser = argparse.ArgumentParser(description='lcfos Compiler')
 parser.add_argument('source', type=argparse.FileType('r'), help='the source file to build')
+parser.add_argument('-d', '--dumpir', action='store_true', help="Dump IR-code")
+parser.add_argument('-o', '--output', help='Output file', metavar='filename')
 args = parser.parse_args()
 
-# Building:
+# Front end:
 src = args.source.read()
 diag = ppci.DiagnosticsManager()
 c3b = c3.Builder(diag)
@@ -17,15 +23,23 @@
     diag.printErrors(src)
     sys.exit(1)
 
-# optionally run passes here:
-# TODO
+if args.dumpir:
+    ircode.dump()
+
+# Code generation:
+
+#cg = codegen.CodeGenerator(arm_cm3.armtarget)
+outs = outstream.TextOutputStream()
+cg = codegenarm.ArmCodeGenerator(outs)
+obj = cg.generate(ircode)
 
-print('stage 3: Code generation')
-asmWriter = core.AsmWriter()
-asmWriter.printModule(module)
+if args.dumpir:
+    outs.dump()
 
-# Generate code:
-bitcodeWriter = core.BitcodeWriter()
-with open(args.source + '.bc', 'wb') as f:
-   bitcodeWriter.WriteModuleToFile(module, f)
+if args.output:
+    output_filename = args.output
+else:
+    output_filename = 'lc.output'
 
+# TODO: store data
+