diff python/arm_cm3.py @ 205:d77cb5962cc5

Added some handcoded arm code generation
author Windel Bouwman
date Sun, 23 Jun 2013 18:23:18 +0200
parents ca1ea402f6a1
children 6c6bf8890d8a
line wrap: on
line diff
--- a/python/arm_cm3.py	Fri Jun 21 15:01:08 2013 +0200
+++ b/python/arm_cm3.py	Sun Jun 23 18:23:18 2013 +0200
@@ -1,11 +1,15 @@
+import struct, types
 from target import Register, Instruction, Target
 from asmnodes import ASymbol, ANumber
 from ppci import CompilerError
-import struct, types
+import ir
 
 def u16(h):
     return struct.pack('<H', h)
 
+def u32(x):
+    return struct.pack('<I', x)
+
 armtarget = Target('arm')
 
 class ArmReg(Register):
@@ -33,6 +37,16 @@
                 r = regs[name]
                 return cls(r.num)
 
+class Label:
+    def __init__(self, name):
+        self.name = name
+
+    @classmethod
+    def Create(cls, vop):
+        if type(vop) is ASymbol:
+            name = vop.name
+            return cls(name)
+
 class Imm8:
     def __init__(self, imm):
         assert imm < 256
@@ -54,7 +68,13 @@
         if type(vop) is ANumber and vop.number < 8:
             return cls(vop.number)
 
+class RegisterSet:
+    def __init__(self, regs):
+        pass
+
 # 8 bit registers:
+r0 = ArmReg(0, 'r0')
+armtarget.registers.append(r0)
 r4 = ArmReg(4, 'r4')
 armtarget.registers.append(r4)
 r5 = ArmReg(5, 'r5')
@@ -71,7 +91,15 @@
 class ldr_ins(ArmInstruction):
     mnemonic = 'ldr'
     opcode = 1337
+    irpattern = 'todo'
 
+@armtarget.instruction
+class dcd_ins(ArmInstruction):
+    mnemonic = 'dcd'
+    def __init__(self, expr):
+        self.expr = expr
+    def encode(self):
+        return u32(self.expr)
 
 class Operand2:
     def __init__(self, expr):
@@ -85,9 +113,15 @@
     mnemonic = 'mov'
     opcode = 4 # 00100 Rd(3) imm8
     operands = (RegOp, Imm8)
+    irpattern = ir.ImmLoad
     def __init__(self, rd, imm):
         self.imm = imm.imm
         self.r = rd.num
+
+    @classmethod
+    def FromIr(cls, ir_ins):
+        pass
+
     def encode(self):
         rd = self.r
         opcode = self.opcode
@@ -121,6 +155,7 @@
     mnemonic = 'add'
     opcode = 3 # 00011
     operands = (RegOp, RegOp, Imm3)
+    irpattern = 3
     def __init__(self, rd, rn, imm3):
         self.rd = rd
         self.rn = rn
@@ -150,6 +185,36 @@
         return u16(h)
 
 @armtarget.instruction
+class jmp_ins(ArmInstruction):
+    operands = (Label)
+    mnemonic = 'jmp'
+    def __init__(self, target_label):
+        self.target = target_label
+    def fixUp(self):
+        pass
+    def encode(self):
+        h = 1337 # TODO
+        return u16(h)
+
+@armtarget.instruction
+class push_ins(ArmInstruction):
+    operands = (RegisterSet)
+    mnemonic = 'push'
+    def __init__(self, regs):
+        self.regs = regs
+    def encode(self):
+        return u16(0)
+
+@armtarget.instruction
+class pop_ins(ArmInstruction):
+    operands = (RegisterSet)
+    mnemonic = 'pop'
+    def __init__(self, regs):
+        self.regs = regs
+    def encode(self):
+        return u16(0)
+
+@armtarget.instruction
 class yield_ins(ArmInstruction):
     operands = ()
     mnemonic = 'yield'