--- a/python/testasm.py	Mon Jul 15 17:20:37 2013 +0200
+++ b/python/testasm.py	Mon Jul 15 20:15:31 2013 +0200
@@ -6,6 +6,8 @@
 from asm import tokenize, Assembler
 import msp430
 import cortexm3 as arm
+import outstream
+from target import Label
 
 class AssemblerLexingCase(unittest.TestCase):
     """ Tests the assemblers lexer """
@@ -42,39 +44,39 @@
         asmline = 'lab1: mov rax, rbx'
         self.a.parse_line(asmline)
 
+    def expectTree(self, asmline, stack):
+        self.a.parse_line(asmline)
+        self.assertSequenceEqual(stack, self.a.stack)
+
     def testParse2(self):
         asmline = 'a: mov rax, [rbx + 2]'
-        self.a.parse_line(asmline)
         output = []
         output.append(ALabel('a'))
         output.append(AInstruction('mov', [ASymbol('rax'), AUnop('[]', ASymbol('rbx') + ANumber(2))]))
-        self.assertSequenceEqual(output, self.a.output)
+        self.expectTree(asmline, output)
 
     def testParse3(self):
         # A label must be optional:
         asmline = 'mov rax, 1'
-        self.a.parse_line(asmline)
         output = [AInstruction('mov', [ASymbol('rax'), ANumber(1)])]
-        self.assertSequenceEqual(output, self.a.output)
+        self.expectTree(asmline, output)
 
     def testParse4(self):
         # Test 3 operands:
         asmline = 'add rax, [4*rbx + 22], rcx'
-        self.a.parse_line(asmline)
         ops = []
         ops.append(ASymbol('rax'))
         ops.append(AUnop('[]', ANumber(4) * ASymbol('rbx') + ANumber(22)))
         ops.append(ASymbol('rcx'))
         output = [AInstruction('add', ops)]
-        self.assertSequenceEqual(output, self.a.output)
+        self.expectTree(asmline, output)
 
     def testParse5(self):
         # An instruction must be optional:
         asmline = 'lab1:'
-        self.a.parse_line(asmline)
         output = []
         output.append(ALabel('lab1'))
-        self.assertSequenceEqual(output, self.a.output)
+        self.expectTree(asmline, output)
 
     def testParse6(self):
         # A line can be empty
@@ -99,10 +101,29 @@
         # Compare with nasm output:
         nasmbytes = [0x48, 0x89, 0xd8, 0x48, 0x31, 0xd9, 0x48, 0xff, 0xc1]
 
-class AssemblerMSP430TestCase(unittest.TestCase):
+
+class OustreamTestCase(unittest.TestCase):
+    def test1(self):
+        o = outstream.BinOutputStream()
+        o.selectSection('.text')
+        o.emit(Label('a'))
+        self.assertSequenceEqual(bytes(), o.Data)
+
+
+class AsmTestCaseBase(unittest.TestCase):
+    def feed(self, line):
+        self.a.assemble(line)
+
+    def check(self, hexstr):
+        self.assertSequenceEqual(bytes.fromhex(hexstr), self.o.Data)
+
+
+class AssemblerMSP430TestCase(AsmTestCaseBase):
     def setUp(self):
         self.t = msp430.msp430target
-        self.a = Assembler(target=self.t)
+        self.o = outstream.BinOutputStream()
+        self.o.selectSection('.text')
+        self.a = Assembler(target=self.t, stream=self.o)
 
     def testMapMovInstruction(self):
         i = AInstruction('mov', [ASymbol('r14'), ASymbol('r15')])
@@ -125,39 +146,35 @@
 
     def testMov(self):
         line1 = "mov r14, r15"
-        self.a.assemble_line(line1)
-        self.assertEqual(bytes([0x0F, 0x4E]), self.a.binout)
+        self.feed(line1)
+        self.check('0F4E')
 
     def testMov1337(self):
         line1 = "mov 0x1337, r12"
-        self.a.assemble_line(line1)
-        self.assertEqual(bytes.fromhex('3C403713'), self.a.binout)
+        self.feed(line1)
+        self.check('3C403713')
 
     def testAdd(self):
         line1 = "add r15, r13"
-        self.a.assemble_line(line1)
-        self.assertEqual(bytes.fromhex('0D5F'), self.a.binout)
+        self.feed(line1)
+        self.check('0D5F')
 
     def testReti(self):
         line1 = "reti"
-        self.a.assemble_line(line1)
-        self.assertEqual(bytes([0x0, 0x13]), self.a.binout)
+        self.feed(line1)
+        self.check('0013')
 
     def testMSPinstructionCount(self):
         """ Check that there are 27 instructions """
         self.assertEqual(27, len(self.t.instructions))
 
 
-class AssemblerARMTestCase(unittest.TestCase):
+class AssemblerARMTestCase(AsmTestCaseBase):
     def setUp(self):
         self.t = arm.armtarget
-        self.a = Assembler(target=self.t)
-
-    def feed(self, line):
-        self.a.assemble(line)
-
-    def check(self, hexstr):
-        self.assertSequenceEqual(bytes.fromhex(hexstr), self.a.binout)
+        self.o = outstream.BinOutputStream()
+        self.o.selectSection('.text')
+        self.a = Assembler(target=self.t, stream=self.o)
 
     def testMapOperand(self):
         pass
@@ -196,9 +213,10 @@
 
     def testLdrPcRel(self):
         self.feed('ldr r1, henkie')
+        self.feed('align 4')
         self.feed('dcd 1')
         self.feed('henkie: dcd 2')
-        self.check('04490100000002000000')
+        self.check('014900000100000002000000')
 
     def testCmpRegReg(self):
         self.feed('cmp r0, r1')