--- a/python/codegenarm.py	Sun Jul 14 12:28:23 2013 +0200
+++ b/python/codegenarm.py	Sun Jul 14 19:29:21 2013 +0200
@@ -1,5 +1,5 @@
 import ir
-from asmnodes import ALabel, AComment
+from target import Label, Comment
 import cortexm3 as arm
 from ppci import CompilerError
 
@@ -37,18 +37,18 @@
                 pass  #self.imms.append((
 
             self.stack_frame = []
-            self.emit(ALabel(f.name))
+            self.emit(Label(f.name))
             # Save some registers:
             self.emit(arm.push_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6,arm.r7,arm.lr})))
             for bb in f.BasicBlocks:
-                self.emit(ALabel(bb.name))
+                self.emit(Label(bb.name))
                 for ins in bb.Instructions:
                     self.generateInstruction(ins)
 
             self.outs.align(4)
             while self.imms:
                 l, v = self.imms.pop()
-                self.emit(ALabel(l))
+                self.emit(Label(l))
                 self.emit(arm.dcd_ins(v))
             self.outs.align(4)
 
@@ -65,16 +65,16 @@
     def loadStack(self, reg, val):
         self.emit(arm.ldr_sprel(reg, arm.MemSpRel(self.getStack(val))))
     def comment(self, txt):
-        self.emit(AComment(txt))
+        self.emit(Comment(txt))
 
     def generateInstruction(self, ins):
         self.comment(str(ins))
         if type(ins) is ir.Branch:
-            tgt = ALabel(ins.target.name)
+            tgt = Label(ins.target.name)
             self.emit(arm.jmp_ins(tgt))
         elif type(ins) is ir.ImmLoad:
             lname = ins.target.name + '_ivalue'
-            self.emit(arm.ldr_pcrel(arm.r0, ALabel(lname)))
+            self.emit(arm.ldr_pcrel(arm.r0, Label(lname)))
             self.imms.append((lname, ins.value))
             self.emit(arm.str_sprel(arm.r0, arm.MemSpRel(self.addStack(ins.target))))
         elif type(ins) is ir.Store: