--- a/python/target/arm.brg	Sun Feb 23 16:24:01 2014 +0100
+++ b/python/target/arm.brg	Fri Feb 28 18:07:14 2014 +0100
@@ -3,7 +3,7 @@
 from target.arminstructions import Orr, Lsl, Str2, Ldr2, Ldr3
 from target.arminstructions import B, Bl, Bgt, Blt, Beq, Bne
 from target.arminstructions import Mov2, Mov3
-from target.arminstructions import Add, Sub, Cmp, Sub2, Add2, Mul
+from target.arminstructions import Add3, Sub, Cmp, Sub2, Add2, Mul
 from ppci import ir
 
 %%
@@ -16,7 +16,7 @@
 %%
 
 
-reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add, dst=[d], src=[$1, $2]); return d .)
+reg: ADDI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Add3, dst=[d], src=[$1, $2]); return d .)
 reg: SUBI32(reg, reg) 2 (. d = self.newTmp(); self.emit(Sub, dst=[d], src=[$1, $2]); return d .)
 reg: ORI32(reg, reg)  2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Orr, dst=[], src=[d, $2]); return d .)
 reg: SHLI32(reg, reg) 2 (. d = self.newTmp(); self.selector.move(d, $1); self.emit(Lsl, dst=[], src=[d, $2]); return d .)