--- a/python/codegenarm.py	Tue Aug 06 18:29:53 2013 +0200
+++ b/python/codegenarm.py	Fri Aug 09 09:05:13 2013 +0200
@@ -3,6 +3,7 @@
 from target import Label, Comment, Alignment, LabelRef, Imm32, DebugInfo
 import cortexm3 as arm
 from ppci import CompilerError
+import irmach
 
 class ArmCodeGenerator:
     """
@@ -19,7 +20,7 @@
     def generate(self, ircode):
         assert isinstance(ircode, ir.Module)
         self.logger.info('Generating arm code for {}'.format(ircode.name))
-        self.available_regs = {arm.r2, arm.r3, arm.r4, arm.r5, arm.r6, arm.r7}
+        self.available_regs = {arm.r3, arm.r4, arm.r5, arm.r6, arm.r7}
         self.regmap = {}
         # TODO: get these from linker descriptor?
         self.outs.getSection('code').address = 0x08000000
@@ -51,7 +52,7 @@
             self.stack_frame = []
             self.emit(Label(f.name))
             # Save some registers:
-            self.emit(arm.push_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6,arm.r7,arm.lr})))
+            self.emit(arm.push_ins(arm.RegisterSet({arm.r3, arm.r4, arm.r5, arm.r6,arm.r7,arm.lr})))
             for bb in f.BasicBlocks:
                 self.emit(Label(bb.name))
                 for ins in bb.Instructions:
@@ -167,7 +168,7 @@
             # TODO: prep parameters:
             self.emit(arm.bl_ins(LabelRef(ins.callee.name)))
         elif type(ins) is ir.Return:
-            self.emit(arm.pop_ins(arm.RegisterSet({arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
+            self.emit(arm.pop_ins(arm.RegisterSet({arm.r3, arm.r4, arm.r5, arm.r6, arm.r7, arm.pc})))
         elif type(ins) is ir.ConditionalBranch:
             r0 = self.getreg(ins.a)
             r1 = self.getreg(ins.b)