--- a/python/x86.py	Fri Mar 08 17:16:22 2013 +0100
+++ b/python/x86.py	Sat Mar 09 11:56:48 2013 +0100
@@ -18,9 +18,14 @@
 class X86CodeGen:
    def __init__(self, diag):
       self.diag = diag
+      self.regs = ['rax', 'rbx', 'rcx', 'rdx']
 
    def emit(self, i):
       self.asm.append(i)
+   def allocateReg(self, typ):
+      return 'ax'
+   def deallocateReg(self, r):
+      pass
 
    def genBin(self, i):
       self.asm = []
@@ -46,8 +51,13 @@
          if i.operation == 'fadd':
             r = 'rax'
             self.emit(Op('add', r, '11'))
+      elif type(i) is ir.LoadInstruction:
+         r = 'rbx'
+         self.emit(Op('mov', r, '{0}'.format(i.value)))
       elif type(i) is ir.RetInstruction:
          self.emit('ret')
+      elif type(i) is ir.CallInstruction:
+         self.emit('call')
       else:
          print('Unknown ins', i)