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comparison doc/compiler.rst @ 274:ea93e0a7a31e
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| author | Windel Bouwman |
|---|---|
| date | Wed, 04 Sep 2013 17:35:06 +0200 |
| parents | python/doc/compiler.rst@6b3a874edd6e |
| children | a6f61e9a9d5c |
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| 273:6b3a874edd6e | 274:ea93e0a7a31e |
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| 1 | |
| 2 | |
| 3 Compiler | |
| 4 ======== | |
| 5 | |
| 6 This chapter describes the design of the compiler. | |
| 7 | |
| 8 | |
| 9 Overview | |
| 10 -------- | |
| 11 | |
| 12 The compiler consists a frontend, mid-end and back-end. The frontend deals with | |
| 13 source file parsing and semantics checking. The mid-end performs optimizations. | |
| 14 This is optional. The back-end generates machine code. The front-end produces | |
| 15 intermediate code. This is a simple representation of the source. The back-end | |
| 16 can accept this kind of representation. This way the compiler is portable and | |
| 17 a front end can be constructed without having to do the rest. | |
| 18 | |
| 19 .. graphviz:: | |
| 20 | |
| 21 digraph x { | |
| 22 rankdir="LR" | |
| 23 1 [label="c3 source file"] | |
| 24 10 [label="c3 front end" ] | |
| 25 11 [label="language X front end" ] | |
| 26 20 [label="mid end" ] | |
| 27 30 [label="back end for X86" ] | |
| 28 31 [label="back end for ARM" ] | |
| 29 40 [label="object file"] | |
| 30 1 -> 10 | |
| 31 10 -> 20 [label="IR-code"] | |
| 32 11 -> 20 [label="IR-code"] | |
| 33 20 -> 30 [label="IR-code"] | |
| 34 20 -> 31 [label="IR-code"] | |
| 35 30 -> 40 | |
| 36 } | |
| 37 | |
| 38 IR-code | |
| 39 ------- | |
| 40 The IR-code is implemented in the ir package. | |
| 41 | |
| 42 .. autoclass:: ir.Module | |
| 43 | |
| 44 .. autoclass:: ir.Function | |
| 45 | |
| 46 .. autoclass:: ir.Block | |
| 47 | |
| 48 .. autoclass:: ir.Statement | |
| 49 | |
| 50 .. autoclass:: ir.Expression | |
| 51 | |
| 52 .. # .. inheritance-diagram:: ir.Statement | |
| 53 | |
| 54 C3 Front-end | |
| 55 ------------ | |
| 56 | |
| 57 For the front-end a recursive descent parser is created for the c3 language. | |
| 58 This is a subset of the C language with some additional features. | |
| 59 | |
| 60 .. graphviz:: | |
| 61 | |
| 62 digraph c3 { | |
| 63 rankdir="LR" | |
| 64 1 [label="source text"] | |
| 65 10 [label="lexer" ] | |
| 66 20 [label="parser" ] | |
| 67 30 [label="semantic checks" ] | |
| 68 40 [label="code generation"] | |
| 69 99 [label="IR-code object"] | |
| 70 1 -> 20 | |
| 71 20 -> 30 | |
| 72 30 -> 40 | |
| 73 40 -> 99 | |
| 74 subgraph rel1 { | |
| 75 edge [dir=none] | |
| 76 10 -> 20 | |
| 77 } | |
| 78 } | |
| 79 | |
| 80 .. autoclass:: c3.Builder | |
| 81 | |
| 82 .. autoclass:: c3.Parser | |
| 83 | |
| 84 .. autoclass:: c3.CodeGenerator | |
| 85 | |
| 86 Back-end | |
| 87 -------- | |
| 88 | |
| 89 The back-end is more complicated. There are several steps to be taken here. | |
| 90 | |
| 91 1. Instruction selection | |
| 92 2. register allocation | |
| 93 3. Peep hole optimization? | |
| 94 4. real code generation | |
| 95 | |
| 96 .. automodule:: codegenarm | |
| 97 :members: | |
| 98 | |
| 99 Instruction selection | |
| 100 ~~~~~~~~~~~~~~~~~~~~~ | |
| 101 | |
| 102 The instruction selection phase takes care of scheduling and instruction | |
| 103 selection. The output of this phase is a one frame per function with a flat | |
| 104 list of abstract machine instructions. | |
| 105 | |
| 106 .. autoclass:: irmach.Frame | |
| 107 | |
| 108 .. autoclass:: irmach.AbstractInstruction | |
| 109 | |
| 110 |