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comparison python/ppci/target/x86/target_x86.py @ 342:86b02c98a717 devel

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Moved target directory
author Windel Bouwman
date Sat, 01 Mar 2014 15:40:31 +0100
parents python/target/target_x86.py@b07d28a5ca56
children c0d9837acde8
comparison
equal deleted inserted replaced
341:4d204f6f7d4e 342:86b02c98a717
1 from target import Register, Instruction, Target
2
3 class x86Register(Register):
4 def __init__(self, name):
5 self.name = name
6
7 class REG16(x86Register):
8 pass
9
10 def addRegs(cls, names):
11 for name in names:
12 r = cls(name)
13 globals()[name] = r
14
15 addRegs(REG16, ['ax', 'bx', 'cx'])
16
17 regs = """
18 ax; reg16
19 """
20
21 class MO:
22 def __init__(self):
23 pass
24
25 instrs = """
26 add; 0x0; mem8/reg8; reg8
27 """
28
29 # machine op table:
30 mot = []
31
32 for i in instrs.split('\n'):
33 i = i.strip()
34 if i:
35 print('INS:', i)
36 mnemonic, opcode, op1, op2 = [a.strip() for a in i.split(';')]
37 print(op1.split('/'), op2.split('/'))
38
39
40 print(mot)
41
42 # Test first with these 3 instructions:
43 """
44 mov reg64, reg64 : opcode=0x89
45 xor reg64, reg64 : opcode=0x31
46 inc reg64 : opcode=0xff
47 """
48
49 class x86Machine:
50 def __init__(self):
51 self.table = []
52 self.table.append((0x0, 'add', 'reg8/mem8, reg8'))
53 self.table.append((0x1, 'add', 'reg16/mem16/reg32/mem32, reg16/reg32'))
54 self.table.append((0x2, 'add', 'reg8, reg8/mem8'))
55 def forMnemonic(self, m):
56 return [i for i in self.table if i[1] == m]
57 def emit(self, m, ops):
58 print(m, ops)
59 ops = self.forMnemonic(m)
60 print(ops)
61
62
63 if __name__ == '__main__':
64 m = x86Machine()
65 m.emit('add', [ax, cx])
66 m.emit('mov', [bx, 1337])